Re: [PATCH v3 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

2017-11-07 Thread Daniel Lezcano
On 07/11/2017 08:19, Rick Chen wrote: > ATCPIT100 is often used on the Andes architecture, > This timer provide 4 PIT channels. Each PIT channel is a > multi-function timer, can be configured as 32,16,8 bit timers > or PWM as well. > > For system timer it will set 32-bit timer0 as clock source >

Re: [PATCH v3 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

2017-11-07 Thread Daniel Lezcano
On 07/11/2017 08:19, Rick Chen wrote: > ATCPIT100 is often used on the Andes architecture, > This timer provide 4 PIT channels. Each PIT channel is a > multi-function timer, can be configured as 32,16,8 bit timers > or PWM as well. > > For system timer it will set 32-bit timer0 as clock source >

[PATCH v3 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

2017-11-06 Thread Rick Chen
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set 32-bit timer0 as clock source and count downwards until underflow and restart

[PATCH v3 1/3] clocksource/drivers/atcpit100: Add andestech atcpit100 timer

2017-11-06 Thread Rick Chen
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set 32-bit timer0 as clock source and count downwards until underflow and restart