Re: [PATCH v3 2/4] clk: bcm2835: Support for clock parent selection

Remi Pommarel writes: > Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple > parent clocks. These clocks divide the rate of a parent which can be selected > by > setting the proper bits in the clock control register. > > Previously all these parents where handled by a

Re: [PATCH v3 2/4] clk: bcm2835: Support for clock parent selection

Remi Pommarel writes: > Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple > parent clocks. These clocks divide the rate of a parent which can be selected > by > setting the proper bits in the clock control register. > > Previously all these parents

[PATCH v3 2/4] clk: bcm2835: Support for clock parent selection

Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parent clocks. These clocks divide the rate of a parent which can be selected by setting the proper bits in the clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot

[PATCH v3 2/4] clk: bcm2835: Support for clock parent selection

Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parent clocks. These clocks divide the rate of a parent which can be selected by setting the proper bits in the clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot