Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 04:51:03PM +0300, Andy Shevchenko wrote: > On Thu, May 28, 2020 at 4:40 PM Serge Semin > wrote: > > > > On Thu, May 28, 2020 at 01:00:57AM +0300, Andy Shevchenko wrote: > > > On Tuesday, May 26, 2020, Serge Semin > > > wrote: > > > > > > > AXI3-bus is the main

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 4:40 PM Serge Semin wrote: > > On Thu, May 28, 2020 at 01:00:57AM +0300, Andy Shevchenko wrote: > > On Tuesday, May 26, 2020, Serge Semin > > wrote: > > > > > AXI3-bus is the main communication bus connecting all high-speed > > > peripheral IP-cores with RAM controller

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 01:00:57AM +0300, Andy Shevchenko wrote: > On Tuesday, May 26, 2020, Serge Semin > wrote: > > > AXI3-bus is the main communication bus connecting all high-speed > > peripheral IP-cores with RAM controller and MIPS P5600 cores on Baikal-T1 > > SoC. Bus traffic arbitration

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 02:44:32PM +0200, Arnd Bergmann wrote: > On Thu, May 28, 2020 at 2:27 PM Serge Semin > wrote: > > > > On Thu, May 28, 2020 at 02:14:58PM +0200, Arnd Bergmann wrote: > > > On Thu, May 28, 2020 at 12:01 AM Andy Shevchenko > > > wrote: > > > > On Tuesday, May 26, 2020, Serge

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 2:27 PM Serge Semin wrote: > > On Thu, May 28, 2020 at 02:14:58PM +0200, Arnd Bergmann wrote: > > On Thu, May 28, 2020 at 12:01 AM Andy Shevchenko > > wrote: > > > On Tuesday, May 26, 2020, Serge Semin > > > wrote: > > >> > > >> AXI3-bus is the main communication bus

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 02:14:58PM +0200, Arnd Bergmann wrote: > On Thu, May 28, 2020 at 12:01 AM Andy Shevchenko > wrote: > > On Tuesday, May 26, 2020, Serge Semin > > wrote: > >> > >> AXI3-bus is the main communication bus connecting all high-speed > >> peripheral IP-cores with RAM controller

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 02:14:58PM +0200, Arnd Bergmann wrote: > On Thu, May 28, 2020 at 12:01 AM Andy Shevchenko > wrote: > > On Tuesday, May 26, 2020, Serge Semin > > wrote: > >> > >> AXI3-bus is the main communication bus connecting all high-speed > >> peripheral IP-cores with RAM controller

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

On Thu, May 28, 2020 at 12:01 AM Andy Shevchenko wrote: > On Tuesday, May 26, 2020, Serge Semin > wrote: >> >> AXI3-bus is the main communication bus connecting all high-speed >> peripheral IP-cores with RAM controller and MIPS P5600 cores on Baikal-T1 >> SoC. Bus traffic arbitration is done by

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

Hi Serge, I love your patch! Yet something to improve: [auto build test ERROR on robh/for-next] [also build test ERROR on char-misc/char-misc-testing staging/staging-testing linus/master v5.7-rc7 next-20200526] [if your patch is applied to the wrong git tree, please drop us a note to help

Re: [PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

Hi Serge, I love your patch! Yet something to improve: [auto build test ERROR on robh/for-next] [also build test ERROR on char-misc/char-misc-testing staging/staging-testing linus/master v5.7-rc7 next-20200526] [if your patch is applied to the wrong git tree, please drop us a note to help

[PATCH v3 4/6] bus: Add Baikal-T1 AXI-bus driver

AXI3-bus is the main communication bus connecting all high-speed peripheral IP-cores with RAM controller and MIPS P5600 cores on Baikal-T1 SoC. Bus traffic arbitration is done by means of DW AMBA 3 AXI Interconnect (so called AXI Main Interconnect) routing IO requests from one SoC block to