Re: [PATCH v4 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

Hi Tuomas, A bunch of small nit picks from me. On Wed, Aug 20, 2014 at 2:04 PM, Tuomas Tynkkynen wrote: > Add shared code to support the Tegra DFLL clocksource in open-loop > mode. This root clocksource is present on the Tegra124 SoCs. The > DFLL is the intended primary clock source for the

Re: [PATCH v4 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

Hi Tuomas, A bunch of small nit picks from me. On Wed, Aug 20, 2014 at 2:04 PM, Tuomas Tynkkynen ttynkky...@nvidia.com wrote: Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock

[PATCH v4 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul Walmsley from December

[PATCH v4 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode)

Add shared code to support the Tegra DFLL clocksource in open-loop mode. This root clocksource is present on the Tegra124 SoCs. The DFLL is the intended primary clock source for the fast CPU cluster. This code is very closely based on a patch by Paul Walmsley from December