Re: [PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

[Stephen Boyd]

Quoting Elaine Zhang (2020-09-13 19:22:20)
> clk_hw_register_composite it's already exported.
> Preparation for compilation of rK common clock drivers into modules.
> 
> Signed-off-by: Elaine Zhang 
> Reported-by: kernel test robot 
> Reviewed-by: Kever Yang 
> Reviewed-by: Heiko Stuebner 
> ---

Reviewed-by: Stephen Boyd 

[PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

[Elaine Zhang]

clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.

Signed-off-by: Elaine Zhang 
Reported-by: kernel test robot 
Reviewed-by: Kever Yang 
Reviewed-by: Heiko Stuebner 
---
 drivers/clk/rockchip/clk-half-divider.c | 18 
 drivers/clk/rockchip/clk.c  | 61 -
 2 files changed, 40 insertions(+), 39 deletions(-)

diff --git a/drivers/clk/rockchip/clk-half-divider.c 
b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
  unsigned long flags,
  spinlock_t *lock)
 {
-   struct clk *clk;
+   struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char 
*name,
div_ops = _half_divider_ops;
}
 
-   clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
+   hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+  mux ? >hw : NULL, mux_ops,
+  div ? >hw : NULL, div_ops,
+  gate ? >hw : NULL, gate_ops,
+  flags);
+   if (IS_ERR(hw))
+   goto err_div;
 
-   return clk;
+   return hw->clk;
 err_div:
kfree(gate);
 err_gate:
kfree(mux);
-   return ERR_PTR(-ENOMEM);
+   return ERR_CAST(hw);
 }
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..46409972983e 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char 
*name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
 {
-   struct clk *clk;
+   struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const 
char *name,
: _divider_ops;
}
 
-   clk = clk_register_composite(NULL, name, parent_names, num_parents,
-mux ? >hw : NULL, mux_ops,
-div ? >hw : NULL, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags);
-
-   if (IS_ERR(clk)) {
-   ret = PTR_ERR(clk);
-   goto err_composite;
+   hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+  mux ? >hw : NULL, mux_ops,
+  div ? >hw : NULL, div_ops,
+  gate ? >hw : NULL, gate_ops,
+  flags);
+   if (IS_ERR(hw)) {
+   kfree(div);
+   kfree(gate);
+   return ERR_CAST(hw);
}
 
-   return clk;
-err_composite:
-   kfree(div);
+   return hw->clk;
 err_div:
kfree(gate);
 err_gate:
@@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
 {
+   struct clk_hw *hw;
struct rockchip_clk_frac *frac;
-   struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = _fractional_divider_ops;
 
-   clk = clk_register_composite(NULL, name, parent_names, num_parents,
-NULL, NULL,
->hw, div_ops,
-gate ? >hw : NULL, gate_ops,
-flags | CLK_SET_RATE_UNGATE);
-   if (IS_ERR(clk)) {
+   hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+  NULL, NULL,
+  >hw, div_ops,
+  gate ? >hw : NULL, gate_ops,
+  flags | CLK_SET_RATE_UNGATE);
+   if