On Mon, 2019-03-11 at 16:21 +0100, Paolo Bonzini wrote:
> On 11/03/19 16:10, Xiaoyao Li wrote:
> > On Mon, 2019-03-11 at 14:31 +0100, Paolo Bonzini wrote:
> > > On 09/03/19 03:31, Xiaoyao Li wrote:
> > > > Hi, Paolo,
> > > >
> > > > Do you have any comments on this patch?
> > > >
> > > > We are
On 11/03/19 16:10, Xiaoyao Li wrote:
> On Mon, 2019-03-11 at 14:31 +0100, Paolo Bonzini wrote:
>> On 09/03/19 03:31, Xiaoyao Li wrote:
>>> Hi, Paolo,
>>>
>>> Do you have any comments on this patch?
>>>
>>> We are preparing v5 patches for split lock detection, if you have any
>>> comments
>>> about
On Mon, 2019-03-11 at 14:31 +0100, Paolo Bonzini wrote:
> On 09/03/19 03:31, Xiaoyao Li wrote:
> > Hi, Paolo,
> >
> > Do you have any comments on this patch?
> >
> > We are preparing v5 patches for split lock detection, if you have any
> > comments
> > about this one, please let me know.
>
>
On 09/03/19 03:31, Xiaoyao Li wrote:
> Hi, Paolo,
>
> Do you have any comments on this patch?
>
> We are preparing v5 patches for split lock detection, if you have any comments
> about this one, please let me know.
No, my only comment is that it should be placed _before_ the other two
for
Hi, Paolo,
Do you have any comments on this patch?
We are preparing v5 patches for split lock detection, if you have any comments
about this one, please let me know.
Thanks,
Xiaoyao
On Fri, 2019-03-01 at 18:45 -0800, Fenghua Yu wrote:
> From: Xiaoyao Li
>
> A control bit (bit 29) in TEST_CTL
From: Xiaoyao Li
A control bit (bit 29) in TEST_CTL MSR 0x33 will be introduced in
future x86 processors. When bit 29 is set, the processor causes #AC
exception for split locked accesses at all CPL.
Please check the latest Intel Software Developer's Manual
for more detailed information on the
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