Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-09-03 Thread Vinod
On 03-09-18, 10:46, Andrea Merello wrote: > Yes, I confirm that here the code does look fine: the 2nd line is > aligned with opening brace indeed. > > Do you want I produce now a v5 with all the other fixes you asked for > (basically commit message fixes), or you are going to apply/check this >

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-09-03 Thread Vinod
On 03-09-18, 10:46, Andrea Merello wrote: > Yes, I confirm that here the code does look fine: the 2nd line is > aligned with opening brace indeed. > > Do you want I produce now a v5 with all the other fixes you asked for > (basically commit message fixes), or you are going to apply/check this >

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-09-03 Thread Andrea Merello
On Thu, Aug 30, 2018 at 3:27 PM Vinod wrote: > > On 30-08-18, 10:11, Andrea Merello wrote: > > On Wed, Aug 29, 2018 at 10:12 AM Andrea Merello > > wrote: > > > > > > On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > > > > > > > On 02-08-18, 16:10, Andrea Merello wrote: > > > > > > > >

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-09-03 Thread Andrea Merello
On Thu, Aug 30, 2018 at 3:27 PM Vinod wrote: > > On 30-08-18, 10:11, Andrea Merello wrote: > > On Wed, Aug 29, 2018 at 10:12 AM Andrea Merello > > wrote: > > > > > > On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > > > > > > > On 02-08-18, 16:10, Andrea Merello wrote: > > > > > > > >

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-30 Thread Vinod
On 30-08-18, 10:11, Andrea Merello wrote: > On Wed, Aug 29, 2018 at 10:12 AM Andrea Merello > wrote: > > > > On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > > > > > On 02-08-18, 16:10, Andrea Merello wrote: > > > > > > s/cylic/cyclic in patch title > > > > OK > > > > > > Whenever a single or

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-30 Thread Vinod
On 30-08-18, 10:11, Andrea Merello wrote: > On Wed, Aug 29, 2018 at 10:12 AM Andrea Merello > wrote: > > > > On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > > > > > On 02-08-18, 16:10, Andrea Merello wrote: > > > > > > s/cylic/cyclic in patch title > > > > OK > > > > > > Whenever a single or

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-30 Thread Andrea Merello
On Wed, Aug 29, 2018 at 10:12 AM Andrea Merello wrote: > > On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > > > On 02-08-18, 16:10, Andrea Merello wrote: > > > > s/cylic/cyclic in patch title > > OK > > > > Whenever a single or cyclic transaction is prepared, the driver > > > could eventually

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-30 Thread Andrea Merello
On Wed, Aug 29, 2018 at 10:12 AM Andrea Merello wrote: > > On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > > > On 02-08-18, 16:10, Andrea Merello wrote: > > > > s/cylic/cyclic in patch title > > OK > > > > Whenever a single or cyclic transaction is prepared, the driver > > > could eventually

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-29 Thread Andrea Merello
On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > On 02-08-18, 16:10, Andrea Merello wrote: > > s/cylic/cyclic in patch title OK > > Whenever a single or cyclic transaction is prepared, the driver > > could eventually split it over several SG descriptors in order > > to deal with the HW maximum

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-29 Thread Andrea Merello
On Mon, Aug 27, 2018 at 7:30 AM Vinod wrote: > > On 02-08-18, 16:10, Andrea Merello wrote: > > s/cylic/cyclic in patch title OK > > Whenever a single or cyclic transaction is prepared, the driver > > could eventually split it over several SG descriptors in order > > to deal with the HW maximum

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-26 Thread Vinod
On 02-08-18, 16:10, Andrea Merello wrote: s/cylic/cyclic in patch title > Whenever a single or cyclic transaction is prepared, the driver > could eventually split it over several SG descriptors in order > to deal with the HW maximum transfer length. > > This could end up in DMA operations

Re: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-26 Thread Vinod
On 02-08-18, 16:10, Andrea Merello wrote: s/cylic/cyclic in patch title > Whenever a single or cyclic transaction is prepared, the driver > could eventually split it over several SG descriptors in order > to deal with the HW maximum transfer length. > > This could end up in DMA operations

[PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-02 Thread Andrea Merello
Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE is not enabled.

[PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors

2018-08-02 Thread Andrea Merello
Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE is not enabled.