Re: [PATCH v4 3/3] i2c: mediatek: Add i2c support for MediaTek MT8183
I am sorry to have missed some comment, and reply the mail again.
On Wed, 2019-02-20 at 15:41 +0100, Matthias Brugger wrote:
>
> On 20/02/2019 13:33, Qii Wang wrote:
> > Add i2c compatible for MT8183. Compare to MT2712 i2c controller,
> > MT8183 has different registers, offsets and clock.
> >
> > Signed-off-by: Qii Wang
>
> So you introduce arb clock, ltiming (what is this exactly) and the new SoC in
> one commit. I'd prefer to split that up and explain shortly in the commit
> message why they are needed. More comments inline.
>
I have split this patch into three in V5.
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 89
> > ---
> > 1 file changed, 84 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c
> > b/drivers/i2c/busses/i2c-mt65xx.c
> > index 428ac99..82eedbd 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -35,6 +35,7 @@
> > #include
> >
> > #define I2C_RS_TRANSFER(1 << 4)
> > +#define I2C_ARB_LOST (1 << 3)
> > #define I2C_HS_NACKERR (1 << 2)
> > #define I2C_ACKERR (1 << 1)
> > #define I2C_TRANSAC_COMP (1 << 0)
> > @@ -76,6 +77,8 @@
> > #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
> > #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
> > #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
> > +#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
> > +#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
> > #define I2C_CONTROL_WRAPPER (0x1 << 0)
> >
> > #define I2C_DRV_NAME "i2c-mt65xx"
> > @@ -130,6 +133,8 @@ enum I2C_REGS_OFFSET {
> > OFFSET_DEBUGCTRL,
> > OFFSET_TRANSFER_LEN_AUX,
> > OFFSET_CLOCK_DIV,
> > + /* MT8183 only regs */
> > + OFFSET_LTIMING,
> > };
> >
> > static const u16 mt_i2c_regs_v1[] = {
> > @@ -159,6 +164,32 @@ enum I2C_REGS_OFFSET {
> > [OFFSET_CLOCK_DIV] = 0x70,
> > };
> >
> > +static const u16 mt_i2c_regs_v2[] = {
> > + [OFFSET_DATA_PORT] = 0x0,
> > + [OFFSET_SLAVE_ADDR] = 0x4,
> > + [OFFSET_INTR_MASK] = 0x8,
> > + [OFFSET_INTR_STAT] = 0xc,
> > + [OFFSET_CONTROL] = 0x10,
> > + [OFFSET_TRANSFER_LEN] = 0x14,
> > + [OFFSET_TRANSAC_LEN] = 0x18,
> > + [OFFSET_DELAY_LEN] = 0x1c,
> > + [OFFSET_TIMING] = 0x20,
> > + [OFFSET_START] = 0x24,
> > + [OFFSET_EXT_CONF] = 0x28,
> > + [OFFSET_LTIMING] = 0x2c,
> > + [OFFSET_HS] = 0x30,
> > + [OFFSET_IO_CONFIG] = 0x34,
> > + [OFFSET_FIFO_ADDR_CLR] = 0x38,
> > + [OFFSET_TRANSFER_LEN_AUX] = 0x44,
> > + [OFFSET_CLOCK_DIV] = 0x48,
> > + [OFFSET_SOFTRESET] = 0x50,
> > + [OFFSET_DEBUGSTAT] = 0xe0,
> > + [OFFSET_DEBUGCTRL] = 0xe8,
> > + [OFFSET_FIFO_STAT] = 0xf4,
> > + [OFFSET_FIFO_THRESH] = 0xf8,
> > + [OFFSET_DCM_EN] = 0xf88,
> > +};
> > +
> > struct mtk_i2c_compatible {
> > const struct i2c_adapter_quirks *quirks;
> > const u16 *regs;
> > @@ -168,6 +199,7 @@ struct mtk_i2c_compatible {
> > unsigned char aux_len_reg: 1;
> > unsigned char support_33bits: 1;
> > unsigned char timing_adjust: 1;
> > + unsigned char dma_sync: 1;
> > };
> >
> > struct mtk_i2c {
> > @@ -181,6 +213,7 @@ struct mtk_i2c {
> > struct clk *clk_main; /* main clock for i2c bus */
> > struct clk *clk_dma;/* DMA clock for i2c via DMA */
> > struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
> > + struct clk *clk_arb;/* Arbitrator clock for i2c */
> > bool have_pmic; /* can use i2c pins from PMIC */
> > bool use_push_pull; /* IO config push-pull mode */
> >
> > @@ -190,6 +223,7 @@ struct mtk_i2c {
> > enum mtk_trans_op op;
> > u16 timing_reg;
> > u16 high_speed_reg;
> > + u16 ltiming_reg;
> > unsigned char auto_restart;
> > bool ignore_restart_irq;
> > const struct mtk_i2c_compatible *dev_comp;
> > @@ -216,6 +250,7 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 1,
> > .timing_adjust = 1,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6577_compat = {
> > @@ -227,6 +262,7 @@ struct mtk_i2c {
> > .aux_len_reg = 0,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6589_compat = {
> > @@ -238,6 +274,7 @@ struct mtk_i2c {
> > .aux_len_reg = 0,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt7622_compat = {
> > @@ -249,6 +286,7 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt8173_compat = {
> > @@ -259,6 +297,18 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 1,
> > .timing_adjust = 0,
> > +
Re: [PATCH v4 3/3] i2c: mediatek: Add i2c support for MediaTek MT8183
On Wed, 2019-02-20 at 15:41 +0100, Matthias Brugger wrote:
>
> On 20/02/2019 13:33, Qii Wang wrote:
> > Add i2c compatible for MT8183. Compare to MT2712 i2c controller,
> > MT8183 has different registers, offsets and clock.
> >
> > Signed-off-by: Qii Wang
>
> So you introduce arb clock, ltiming (what is this exactly) and the new SoC in
> one commit. I'd prefer to split that up and explain shortly in the commit
> message why they are needed. More comments inline.
>
Sounds good to me. If there is no other comments, I will split this
patch into three, arb clock, dma_sync and the new SoC. ltiming is a new
design for the new SoC, I think it is better to put in one patch.
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 89
> > ---
> > 1 file changed, 84 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c
> > b/drivers/i2c/busses/i2c-mt65xx.c
> > index 428ac99..82eedbd 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -35,6 +35,7 @@
> > #include
> >
> > #define I2C_RS_TRANSFER(1 << 4)
> > +#define I2C_ARB_LOST (1 << 3)
> > #define I2C_HS_NACKERR (1 << 2)
> > #define I2C_ACKERR (1 << 1)
> > #define I2C_TRANSAC_COMP (1 << 0)
> > @@ -76,6 +77,8 @@
> > #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
> > #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
> > #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
> > +#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
> > +#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
> > #define I2C_CONTROL_WRAPPER (0x1 << 0)
> >
> > #define I2C_DRV_NAME "i2c-mt65xx"
> > @@ -130,6 +133,8 @@ enum I2C_REGS_OFFSET {
> > OFFSET_DEBUGCTRL,
> > OFFSET_TRANSFER_LEN_AUX,
> > OFFSET_CLOCK_DIV,
> > + /* MT8183 only regs */
> > + OFFSET_LTIMING,
> > };
> >
> > static const u16 mt_i2c_regs_v1[] = {
> > @@ -159,6 +164,32 @@ enum I2C_REGS_OFFSET {
> > [OFFSET_CLOCK_DIV] = 0x70,
> > };
> >
> > +static const u16 mt_i2c_regs_v2[] = {
> > + [OFFSET_DATA_PORT] = 0x0,
> > + [OFFSET_SLAVE_ADDR] = 0x4,
> > + [OFFSET_INTR_MASK] = 0x8,
> > + [OFFSET_INTR_STAT] = 0xc,
> > + [OFFSET_CONTROL] = 0x10,
> > + [OFFSET_TRANSFER_LEN] = 0x14,
> > + [OFFSET_TRANSAC_LEN] = 0x18,
> > + [OFFSET_DELAY_LEN] = 0x1c,
> > + [OFFSET_TIMING] = 0x20,
> > + [OFFSET_START] = 0x24,
> > + [OFFSET_EXT_CONF] = 0x28,
> > + [OFFSET_LTIMING] = 0x2c,
> > + [OFFSET_HS] = 0x30,
> > + [OFFSET_IO_CONFIG] = 0x34,
> > + [OFFSET_FIFO_ADDR_CLR] = 0x38,
> > + [OFFSET_TRANSFER_LEN_AUX] = 0x44,
> > + [OFFSET_CLOCK_DIV] = 0x48,
> > + [OFFSET_SOFTRESET] = 0x50,
> > + [OFFSET_DEBUGSTAT] = 0xe0,
> > + [OFFSET_DEBUGCTRL] = 0xe8,
> > + [OFFSET_FIFO_STAT] = 0xf4,
> > + [OFFSET_FIFO_THRESH] = 0xf8,
> > + [OFFSET_DCM_EN] = 0xf88,
> > +};
> > +
> > struct mtk_i2c_compatible {
> > const struct i2c_adapter_quirks *quirks;
> > const u16 *regs;
> > @@ -168,6 +199,7 @@ struct mtk_i2c_compatible {
> > unsigned char aux_len_reg: 1;
> > unsigned char support_33bits: 1;
> > unsigned char timing_adjust: 1;
> > + unsigned char dma_sync: 1;
> > };
> >
> > struct mtk_i2c {
> > @@ -181,6 +213,7 @@ struct mtk_i2c {
> > struct clk *clk_main; /* main clock for i2c bus */
> > struct clk *clk_dma;/* DMA clock for i2c via DMA */
> > struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
> > + struct clk *clk_arb;/* Arbitrator clock for i2c */
> > bool have_pmic; /* can use i2c pins from PMIC */
> > bool use_push_pull; /* IO config push-pull mode */
> >
> > @@ -190,6 +223,7 @@ struct mtk_i2c {
> > enum mtk_trans_op op;
> > u16 timing_reg;
> > u16 high_speed_reg;
> > + u16 ltiming_reg;
> > unsigned char auto_restart;
> > bool ignore_restart_irq;
> > const struct mtk_i2c_compatible *dev_comp;
> > @@ -216,6 +250,7 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 1,
> > .timing_adjust = 1,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6577_compat = {
> > @@ -227,6 +262,7 @@ struct mtk_i2c {
> > .aux_len_reg = 0,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6589_compat = {
> > @@ -238,6 +274,7 @@ struct mtk_i2c {
> > .aux_len_reg = 0,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt7622_compat = {
> > @@ -249,6 +286,7 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt8173_compat = {
> > @@ -259,6 +297,18 @@ struct mtk_i2c {
Re: [PATCH v4 3/3] i2c: mediatek: Add i2c support for MediaTek MT8183
On 20/02/2019 13:33, Qii Wang wrote:
> Add i2c compatible for MT8183. Compare to MT2712 i2c controller,
> MT8183 has different registers, offsets and clock.
>
> Signed-off-by: Qii Wang
So you introduce arb clock, ltiming (what is this exactly) and the new SoC in
one commit. I'd prefer to split that up and explain shortly in the commit
message why they are needed. More comments inline.
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 89
> ---
> 1 file changed, 84 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index 428ac99..82eedbd 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -35,6 +35,7 @@
> #include
>
> #define I2C_RS_TRANSFER (1 << 4)
> +#define I2C_ARB_LOST (1 << 3)
> #define I2C_HS_NACKERR (1 << 2)
> #define I2C_ACKERR (1 << 1)
> #define I2C_TRANSAC_COMP (1 << 0)
> @@ -76,6 +77,8 @@
> #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
> #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
> #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
> +#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
> +#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
> #define I2C_CONTROL_WRAPPER (0x1 << 0)
>
> #define I2C_DRV_NAME "i2c-mt65xx"
> @@ -130,6 +133,8 @@ enum I2C_REGS_OFFSET {
> OFFSET_DEBUGCTRL,
> OFFSET_TRANSFER_LEN_AUX,
> OFFSET_CLOCK_DIV,
> + /* MT8183 only regs */
> + OFFSET_LTIMING,
> };
>
> static const u16 mt_i2c_regs_v1[] = {
> @@ -159,6 +164,32 @@ enum I2C_REGS_OFFSET {
> [OFFSET_CLOCK_DIV] = 0x70,
> };
>
> +static const u16 mt_i2c_regs_v2[] = {
> + [OFFSET_DATA_PORT] = 0x0,
> + [OFFSET_SLAVE_ADDR] = 0x4,
> + [OFFSET_INTR_MASK] = 0x8,
> + [OFFSET_INTR_STAT] = 0xc,
> + [OFFSET_CONTROL] = 0x10,
> + [OFFSET_TRANSFER_LEN] = 0x14,
> + [OFFSET_TRANSAC_LEN] = 0x18,
> + [OFFSET_DELAY_LEN] = 0x1c,
> + [OFFSET_TIMING] = 0x20,
> + [OFFSET_START] = 0x24,
> + [OFFSET_EXT_CONF] = 0x28,
> + [OFFSET_LTIMING] = 0x2c,
> + [OFFSET_HS] = 0x30,
> + [OFFSET_IO_CONFIG] = 0x34,
> + [OFFSET_FIFO_ADDR_CLR] = 0x38,
> + [OFFSET_TRANSFER_LEN_AUX] = 0x44,
> + [OFFSET_CLOCK_DIV] = 0x48,
> + [OFFSET_SOFTRESET] = 0x50,
> + [OFFSET_DEBUGSTAT] = 0xe0,
> + [OFFSET_DEBUGCTRL] = 0xe8,
> + [OFFSET_FIFO_STAT] = 0xf4,
> + [OFFSET_FIFO_THRESH] = 0xf8,
> + [OFFSET_DCM_EN] = 0xf88,
> +};
> +
> struct mtk_i2c_compatible {
> const struct i2c_adapter_quirks *quirks;
> const u16 *regs;
> @@ -168,6 +199,7 @@ struct mtk_i2c_compatible {
> unsigned char aux_len_reg: 1;
> unsigned char support_33bits: 1;
> unsigned char timing_adjust: 1;
> + unsigned char dma_sync: 1;
> };
>
> struct mtk_i2c {
> @@ -181,6 +213,7 @@ struct mtk_i2c {
> struct clk *clk_main; /* main clock for i2c bus */
> struct clk *clk_dma;/* DMA clock for i2c via DMA */
> struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
> + struct clk *clk_arb;/* Arbitrator clock for i2c */
> bool have_pmic; /* can use i2c pins from PMIC */
> bool use_push_pull; /* IO config push-pull mode */
>
> @@ -190,6 +223,7 @@ struct mtk_i2c {
> enum mtk_trans_op op;
> u16 timing_reg;
> u16 high_speed_reg;
> + u16 ltiming_reg;
> unsigned char auto_restart;
> bool ignore_restart_irq;
> const struct mtk_i2c_compatible *dev_comp;
> @@ -216,6 +250,7 @@ struct mtk_i2c {
> .aux_len_reg = 1,
> .support_33bits = 1,
> .timing_adjust = 1,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -227,6 +262,7 @@ struct mtk_i2c {
> .aux_len_reg = 0,
> .support_33bits = 0,
> .timing_adjust = 0,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -238,6 +274,7 @@ struct mtk_i2c {
> .aux_len_reg = 0,
> .support_33bits = 0,
> .timing_adjust = 0,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -249,6 +286,7 @@ struct mtk_i2c {
> .aux_len_reg = 1,
> .support_33bits = 0,
> .timing_adjust = 0,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -259,6 +297,18 @@ struct mtk_i2c {
> .aux_len_reg = 1,
> .support_33bits = 1,
> .timing_adjust = 0,
> + .dma_sync = 0,
> +};
> +
> +static const struct mtk_i2c_compatible mt8183_compat = {
> + .regs = mt_i2c_regs_v2,
> + .pmic_i2c = 0,
> + .dcm = 0,
> + .auto_restart = 1,
> + .aux_len_reg = 1,
> + .support_33bits = 1,
> + .timing_adjust = 1,
> + .dma_sync = 1,
> };
>
> static const struct
[PATCH v4 3/3] i2c: mediatek: Add i2c support for MediaTek MT8183
Add i2c compatible for MT8183. Compare to MT2712 i2c controller,
MT8183 has different registers, offsets and clock.
Signed-off-by: Qii Wang
---
drivers/i2c/busses/i2c-mt65xx.c | 89 ---
1 file changed, 84 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 428ac99..82eedbd 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -35,6 +35,7 @@
#include
#define I2C_RS_TRANSFER(1 << 4)
+#define I2C_ARB_LOST (1 << 3)
#define I2C_HS_NACKERR (1 << 2)
#define I2C_ACKERR (1 << 1)
#define I2C_TRANSAC_COMP (1 << 0)
@@ -76,6 +77,8 @@
#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
+#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
+#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
#define I2C_CONTROL_WRAPPER (0x1 << 0)
#define I2C_DRV_NAME "i2c-mt65xx"
@@ -130,6 +133,8 @@ enum I2C_REGS_OFFSET {
OFFSET_DEBUGCTRL,
OFFSET_TRANSFER_LEN_AUX,
OFFSET_CLOCK_DIV,
+ /* MT8183 only regs */
+ OFFSET_LTIMING,
};
static const u16 mt_i2c_regs_v1[] = {
@@ -159,6 +164,32 @@ enum I2C_REGS_OFFSET {
[OFFSET_CLOCK_DIV] = 0x70,
};
+static const u16 mt_i2c_regs_v2[] = {
+ [OFFSET_DATA_PORT] = 0x0,
+ [OFFSET_SLAVE_ADDR] = 0x4,
+ [OFFSET_INTR_MASK] = 0x8,
+ [OFFSET_INTR_STAT] = 0xc,
+ [OFFSET_CONTROL] = 0x10,
+ [OFFSET_TRANSFER_LEN] = 0x14,
+ [OFFSET_TRANSAC_LEN] = 0x18,
+ [OFFSET_DELAY_LEN] = 0x1c,
+ [OFFSET_TIMING] = 0x20,
+ [OFFSET_START] = 0x24,
+ [OFFSET_EXT_CONF] = 0x28,
+ [OFFSET_LTIMING] = 0x2c,
+ [OFFSET_HS] = 0x30,
+ [OFFSET_IO_CONFIG] = 0x34,
+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
+ [OFFSET_TRANSFER_LEN_AUX] = 0x44,
+ [OFFSET_CLOCK_DIV] = 0x48,
+ [OFFSET_SOFTRESET] = 0x50,
+ [OFFSET_DEBUGSTAT] = 0xe0,
+ [OFFSET_DEBUGCTRL] = 0xe8,
+ [OFFSET_FIFO_STAT] = 0xf4,
+ [OFFSET_FIFO_THRESH] = 0xf8,
+ [OFFSET_DCM_EN] = 0xf88,
+};
+
struct mtk_i2c_compatible {
const struct i2c_adapter_quirks *quirks;
const u16 *regs;
@@ -168,6 +199,7 @@ struct mtk_i2c_compatible {
unsigned char aux_len_reg: 1;
unsigned char support_33bits: 1;
unsigned char timing_adjust: 1;
+ unsigned char dma_sync: 1;
};
struct mtk_i2c {
@@ -181,6 +213,7 @@ struct mtk_i2c {
struct clk *clk_main; /* main clock for i2c bus */
struct clk *clk_dma;/* DMA clock for i2c via DMA */
struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
+ struct clk *clk_arb;/* Arbitrator clock for i2c */
bool have_pmic; /* can use i2c pins from PMIC */
bool use_push_pull; /* IO config push-pull mode */
@@ -190,6 +223,7 @@ struct mtk_i2c {
enum mtk_trans_op op;
u16 timing_reg;
u16 high_speed_reg;
+ u16 ltiming_reg;
unsigned char auto_restart;
bool ignore_restart_irq;
const struct mtk_i2c_compatible *dev_comp;
@@ -216,6 +250,7 @@ struct mtk_i2c {
.aux_len_reg = 1,
.support_33bits = 1,
.timing_adjust = 1,
+ .dma_sync = 0,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -227,6 +262,7 @@ struct mtk_i2c {
.aux_len_reg = 0,
.support_33bits = 0,
.timing_adjust = 0,
+ .dma_sync = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -238,6 +274,7 @@ struct mtk_i2c {
.aux_len_reg = 0,
.support_33bits = 0,
.timing_adjust = 0,
+ .dma_sync = 0,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -249,6 +286,7 @@ struct mtk_i2c {
.aux_len_reg = 1,
.support_33bits = 0,
.timing_adjust = 0,
+ .dma_sync = 0,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -259,6 +297,18 @@ struct mtk_i2c {
.aux_len_reg = 1,
.support_33bits = 1,
.timing_adjust = 0,
+ .dma_sync = 0,
+};
+
+static const struct mtk_i2c_compatible mt8183_compat = {
+ .regs = mt_i2c_regs_v2,
+ .pmic_i2c = 0,
+ .dcm = 0,
+ .auto_restart = 1,
+ .aux_len_reg = 1,
+ .support_33bits = 1,
+ .timing_adjust = 1,
+ .dma_sync = 1,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -267,6 +317,7 @@ struct mtk_i2c {
{ .compatible = "mediatek,mt6589-i2c", .data = _compat },
{ .compatible = "mediatek,mt7622-i2c", .data = _compat },
{ .compatible = "mediatek,mt8173-i2c", .data = _compat },
+ { .compatible = "mediatek,mt8183-i2c", .data = _compat },
{}
};
MODULE_DEVICE_TABLE(of,
