On Tuesday, April 29, 2014 11:45 PM, Catalin Marinas wrote:
> On Tue, Apr 29, 2014 at 05:59:23AM +0100, Jungseok Lee wrote:
> > +config ARM64_VA_BITS
> > + int "Virtual address space size"
> > + range 39 39 if ARM64_4K_PAGES && ARM64_3_LEVELS
> > + range 42 42 if ARM64_64K_PAGES &&
On Tue, Apr 29, 2014 at 05:59:23AM +0100, Jungseok Lee wrote:
> +config ARM64_VA_BITS
> + int "Virtual address space size"
> + range 39 39 if ARM64_4K_PAGES && ARM64_3_LEVELS
> + range 42 42 if ARM64_64K_PAGES && ARM64_2_LEVELS
> + help
> + This feature is determined by a
On Tue, Apr 29, 2014 at 05:59:23AM +0100, Jungseok Lee wrote:
+config ARM64_VA_BITS
+ int Virtual address space size
+ range 39 39 if ARM64_4K_PAGES ARM64_3_LEVELS
+ range 42 42 if ARM64_64K_PAGES ARM64_2_LEVELS
+ help
+ This feature is determined by a combination of
On Tuesday, April 29, 2014 11:45 PM, Catalin Marinas wrote:
On Tue, Apr 29, 2014 at 05:59:23AM +0100, Jungseok Lee wrote:
+config ARM64_VA_BITS
+ int Virtual address space size
+ range 39 39 if ARM64_4K_PAGES ARM64_3_LEVELS
+ range 42 42 if ARM64_64K_PAGES ARM64_2_LEVELS
+
This patch adds a kernel configuration for VA_BITS.
It helps to prevent unnecessary #ifdef statements insertions
for VA_BITS when implementing different page sizes and level of
translation tables.
Cc: Catalin Marinas
Cc: Steve Capper
Signed-off-by: Jungseok Lee
Reviewed-by: Sungjinn Chung
This patch adds a kernel configuration for VA_BITS.
It helps to prevent unnecessary #ifdef statements insertions
for VA_BITS when implementing different page sizes and level of
translation tables.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Steve Capper steve.cap...@linaro.org
Signed-off-by:
6 matches
Mail list logo
