On Thu, Jan 09, 2014 at 08:52:21PM +, Stephen Boyd wrote:
> On 01/08/14 02:05, Lorenzo Pieralisi wrote:
> > On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
> >> On 01/07, Lorenzo Pieralisi wrote:
> >>
> >>> I have a problem with the cache level definition, and in
> >>> particular
On Thu, Jan 09, 2014 at 08:52:21PM +, Stephen Boyd wrote:
On 01/08/14 02:05, Lorenzo Pieralisi wrote:
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
I have a problem with the cache level definition, and in
particular the numbering,
On 01/08/14 02:05, Lorenzo Pieralisi wrote:
> On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
>> On 01/07, Lorenzo Pieralisi wrote:
>>
>>> I have a problem with the cache level definition, and in
>>> particular the numbering, ie what the level number represents. If we
>>> mean the
On 01/08/14 02:05, Lorenzo Pieralisi wrote:
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
I have a problem with the cache level definition, and in
particular the numbering, ie what the level number represents. If we
mean the cache level seen
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
> On 01/07, Lorenzo Pieralisi wrote:
> >
> > Not sure this binding (cache node) belongs in cpus.txt
> >
> > I am working on defining cache bindings for ARM within the C-state
> > standardization effort:
> >
> >
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
Not sure this binding (cache node) belongs in cpus.txt
I am working on defining cache bindings for ARM within the C-state
standardization effort:
On 01/07, Lorenzo Pieralisi wrote:
>
> Not sure this binding (cache node) belongs in cpus.txt
>
> I am working on defining cache bindings for ARM within the C-state
> standardization effort:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2013-December/215543.html
Thanks I'll take a
On Mon, Dec 30, 2013 at 08:14:15PM +, Stephen Boyd wrote:
> The Krait L1/L2 error reporting device is made up of two
> interrupts, one per-CPU interrupt for the L1 caches and one
> interrupt for the L2 cache.
>
> Cc: Lorenzo Pieralisi
> Cc: Mark Rutland
> Cc: Kumar Gala
> Cc:
>
On Mon, Dec 30, 2013 at 08:14:15PM +, Stephen Boyd wrote:
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland
On 01/07, Lorenzo Pieralisi wrote:
Not sure this binding (cache node) belongs in cpus.txt
I am working on defining cache bindings for ARM within the C-state
standardization effort:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-December/215543.html
Thanks I'll take a look.
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi
Cc: Mark Rutland
Cc: Kumar Gala
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/cpus.txt | 72
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Kumar Gala ga...@codeaurora.org
Cc: devicet...@vger.kernel.org
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