On Fri, Apr 25, 2014 at 06:04:19PM +0200, Peter Zijlstra wrote:
> > The example above is consistent because CPU2 mask and CPU0 mask are
> > fully exclusive
> >
> > so
> > CPU0: cpu_corepower_mask=0-1
> > CPU2: cpu_corepower_mask=2
> > are consistent
> >
> > CPU0: cpu_corepower_mask=0-2
> > CPU2:
> The example above is consistent because CPU2 mask and CPU0 mask are
> fully exclusive
>
> so
> CPU0: cpu_corepower_mask=0-1
> CPU2: cpu_corepower_mask=2
> are consistent
>
> CPU0: cpu_corepower_mask=0-2
> CPU2: cpu_corepower_mask=0-2
> are also consistent
>
> but
>
> CPU0: cpu_corepower_mask=
On 25/04/14 08:45, Vincent Guittot wrote:
[...]
>>
>> Back than I had
>> CPU0: cpu_corepower_mask=0-1
>> CPU2: cpu_corepower_mask=2
>> so for GMC level the cpumasks are inconsistent across CPUs and it worked.
>
> The example above is consistent because CPU2 mask and CPU0 mask are
> fully exc
On 24 April 2014 14:48, Dietmar Eggemann wrote:
> On 24/04/14 08:30, Vincent Guittot wrote:
>> On 23 April 2014 17:26, Dietmar Eggemann wrote:
>>> On 23/04/14 15:46, Vincent Guittot wrote:
On 23 April 2014 13:46, Dietmar Eggemann wrote:
> Hi,
>
> [...]
>
>>
>> More than the flag that is
On 24/04/14 08:30, Vincent Guittot wrote:
> On 23 April 2014 17:26, Dietmar Eggemann wrote:
>> On 23/04/14 15:46, Vincent Guittot wrote:
>>> On 23 April 2014 13:46, Dietmar Eggemann wrote:
Hi,
[...]
>
> More than the flag that is used for the example, it's about the
> cpumask which are in
On 23 April 2014 17:26, Dietmar Eggemann wrote:
> On 23/04/14 15:46, Vincent Guittot wrote:
>> On 23 April 2014 13:46, Dietmar Eggemann wrote:
>>> Hi,
>>>
[snip]
>> You have an inconsistency in your topology description:
>
> That's true functional-wise but I think that this is not the reason w
On 23/04/14 15:46, Vincent Guittot wrote:
> On 23 April 2014 13:46, Dietmar Eggemann wrote:
>> Hi,
>>
>> I'm trying to use this approach of specifying different per-cpu views on
>> sd flags on DIE level on a TC2 platform (cluster 0 w/ CPU0/1 and cluster
>> 1 w/ CPU2/3/4 w/o SMT). It doesn't work l
On 23 April 2014 13:46, Dietmar Eggemann wrote:
> Hi,
>
> I'm trying to use this approach of specifying different per-cpu views on
> sd flags on DIE level on a TC2 platform (cluster 0 w/ CPU0/1 and cluster
> 1 w/ CPU2/3/4 w/o SMT). It doesn't work like in the case for the GMC/MC
> sd level.
>
> If
Hi,
I'm trying to use this approach of specifying different per-cpu views on
sd flags on DIE level on a TC2 platform (cluster 0 w/ CPU0/1 and cluster
1 w/ CPU2/3/4 w/o SMT). It doesn't work like in the case for the GMC/MC
sd level.
If I use the following patch (just to illustrate the issue) on to
Create a dedicated topology table for ARM which will create new level to
differentiate CPUs that can or not powergate independantly from others.
The patch gives an example of how to add domain that will take advantage of
SD_SHARE_POWERDOMAIN.
Signed-off-by: Vincent Guittot
---
arch/arm/kernel/t
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