Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-08-06 Thread Bjorn Helgaas
On Mon, Aug 6, 2018 at 1:39 PM wrote: > > On 08/05/2018 02:06 AM, Tal Gilboa wrote: > > On 7/31/2018 6:10 PM, Alex G. wrote: > >> On 07/31/2018 01:40 AM, Tal Gilboa wrote: > >> [snip] > >> @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct > >> pci_dev *dev) > >>/*

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-08-06 Thread Bjorn Helgaas
On Mon, Aug 6, 2018 at 1:39 PM wrote: > > On 08/05/2018 02:06 AM, Tal Gilboa wrote: > > On 7/31/2018 6:10 PM, Alex G. wrote: > >> On 07/31/2018 01:40 AM, Tal Gilboa wrote: > >> [snip] > >> @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct > >> pci_dev *dev) > >>/*

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-08-06 Thread Alex_Gagniuc
On 08/05/2018 02:06 AM, Tal Gilboa wrote: > On 7/31/2018 6:10 PM, Alex G. wrote: >> On 07/31/2018 01:40 AM, Tal Gilboa wrote: >> [snip] >> @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct >> pci_dev *dev) >>   /* Advanced Error Reporting */ >>  

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-08-06 Thread Alex_Gagniuc
On 08/05/2018 02:06 AM, Tal Gilboa wrote: > On 7/31/2018 6:10 PM, Alex G. wrote: >> On 07/31/2018 01:40 AM, Tal Gilboa wrote: >> [snip] >> @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct >> pci_dev *dev) >>   /* Advanced Error Reporting */ >>  

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-08-05 Thread Tal Gilboa
On 7/31/2018 6:10 PM, Alex G. wrote: On 07/31/2018 01:40 AM, Tal Gilboa wrote: [snip] @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct pci_dev *dev)   /* Advanced Error Reporting */   pci_aer_init(dev); +    /* Check link and detect downtrain errors */ +   

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-08-05 Thread Tal Gilboa
On 7/31/2018 6:10 PM, Alex G. wrote: On 07/31/2018 01:40 AM, Tal Gilboa wrote: [snip] @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct pci_dev *dev)   /* Advanced Error Reporting */   pci_aer_init(dev); +    /* Check link and detect downtrain errors */ +   

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-31 Thread Alex G.
On 07/31/2018 01:40 AM, Tal Gilboa wrote: [snip] @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct pci_dev *dev)   /* Advanced Error Reporting */   pci_aer_init(dev); +    /* Check link and detect downtrain errors */ +    pcie_check_upstream_link(dev); This is called for

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-31 Thread Alex G.
On 07/31/2018 01:40 AM, Tal Gilboa wrote: [snip] @@ -2240,6 +2258,9 @@ static void pci_init_capabilities(struct pci_dev *dev)   /* Advanced Error Reporting */   pci_aer_init(dev); +    /* Check link and detect downtrain errors */ +    pcie_check_upstream_link(dev); This is called for

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-31 Thread Tal Gilboa
On 7/24/2018 12:52 AM, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device and PCIe port are capable of a larger bus width or higher speed than negotiated. Downtraining might

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-31 Thread Tal Gilboa
On 7/24/2018 12:52 AM, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device and PCIe port are capable of a larger bus width or higher speed than negotiated. Downtraining might

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-30 Thread Alex_Gagniuc
On 07/24/2018 08:40 AM, Tal Gilboa wrote: > On 7/24/2018 2:59 AM, Alex G. wrote: >> >> >> On 07/23/2018 05:14 PM, Jakub Kicinski wrote: >>> On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: > On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-30 Thread Alex_Gagniuc
On 07/24/2018 08:40 AM, Tal Gilboa wrote: > On 7/24/2018 2:59 AM, Alex G. wrote: >> >> >> On 07/23/2018 05:14 PM, Jakub Kicinski wrote: >>> On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: > On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-24 Thread Tal Gilboa
On 7/24/2018 2:59 AM, Alex G. wrote: On 07/23/2018 05:14 PM, Jakub Kicinski wrote: On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-24 Thread Tal Gilboa
On 7/24/2018 2:59 AM, Alex G. wrote: On 07/23/2018 05:14 PM, Jakub Kicinski wrote: On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Alex G.
On 07/23/2018 05:14 PM, Jakub Kicinski wrote: On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device and PCIe port are capable of a larger

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Alex G.
On 07/23/2018 05:14 PM, Jakub Kicinski wrote: On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device and PCIe port are capable of a larger

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Jakub Kicinski
On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: > On 7/24/2018 12:01 AM, Jakub Kicinski wrote: > > On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: > >> PCIe downtraining happens when both the device and PCIe port are > >> capable of a larger bus width or higher speed than

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Jakub Kicinski
On Tue, 24 Jul 2018 00:52:22 +0300, Tal Gilboa wrote: > On 7/24/2018 12:01 AM, Jakub Kicinski wrote: > > On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: > >> PCIe downtraining happens when both the device and PCIe port are > >> capable of a larger bus width or higher speed than

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Tal Gilboa
On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device and PCIe port are capable of a larger bus width or higher speed than negotiated. Downtraining might be indicative of other problems in the

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Tal Gilboa
On 7/24/2018 12:01 AM, Jakub Kicinski wrote: On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: PCIe downtraining happens when both the device and PCIe port are capable of a larger bus width or higher speed than negotiated. Downtraining might be indicative of other problems in the

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Jakub Kicinski
On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: > PCIe downtraining happens when both the device and PCIe port are > capable of a larger bus width or higher speed than negotiated. > Downtraining might be indicative of other problems in the system, and > identifying this from userspace

Re: [PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Jakub Kicinski
On Mon, 23 Jul 2018 15:03:38 -0500, Alexandru Gagniuc wrote: > PCIe downtraining happens when both the device and PCIe port are > capable of a larger bus width or higher speed than negotiated. > Downtraining might be indicative of other problems in the system, and > identifying this from userspace

[PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Alexandru Gagniuc
PCIe downtraining happens when both the device and PCIe port are capable of a larger bus width or higher speed than negotiated. Downtraining might be indicative of other problems in the system, and identifying this from userspace is neither intuitive, nor straightforward. The easiest way to

[PATCH v5] PCI: Check for PCIe downtraining conditions

2018-07-23 Thread Alexandru Gagniuc
PCIe downtraining happens when both the device and PCIe port are capable of a larger bus width or higher speed than negotiated. Downtraining might be indicative of other problems in the system, and identifying this from userspace is neither intuitive, nor straightforward. The easiest way to