On 23/01/15 17:25, Mark Rutland wrote:
> Hi Daniel,
>
> On Tue, Jan 20, 2015 at 12:25:35PM +, Daniel Thompson wrote:
>> Some ARM platforms mux the PMU interrupt of every core into a single
>> SPI. On such platforms if the PMU of any core except 0 raises an interrupt
>> then it cannot be
On 23/01/15 17:25, Mark Rutland wrote:
Hi Daniel,
On Tue, Jan 20, 2015 at 12:25:35PM +, Daniel Thompson wrote:
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and
Hi Daniel,
On Tue, Jan 20, 2015 at 12:25:35PM +, Daniel Thompson wrote:
> Some ARM platforms mux the PMU interrupt of every core into a single
> SPI. On such platforms if the PMU of any core except 0 raises an interrupt
> then it cannot be serviced and eventually, if you are lucky, the
Hi Daniel,
On Tue, Jan 20, 2015 at 12:25:35PM +, Daniel Thompson wrote:
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
irq detection might forcefully disable the interrupt.
On these SoCs it is not
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
irq detection might forcefully disable the interrupt.
On these SoCs it is not
6 matches
Mail list logo
