On 02/15/2019 09:10 PM, Andi Kleen wrote:
OK. The freeze bits need to be cleared by IA32_PERF_GLOBAL_STATUS_RESET, which
seems not supported by the perf code yet (thus guest won't clear them). Would
handle_irq_v4 also need to be changed to support that?
In Arch Perfmon v4 it is cleared by
On Fri, Feb 15, 2019 at 08:56:02AM +, Wang, Wei W wrote:
> On Friday, February 15, 2019 12:32 AM, Andi Kleen wrote:
> >
> > > +static void intel_pmu_get_global_status(struct kvm_pmu *pmu,
> > > + struct msr_data *msr_info)
> > > +{
> > > + u64 guest_debugctl,
On Friday, February 15, 2019 12:32 AM, Andi Kleen wrote:
>
> > +static void intel_pmu_get_global_status(struct kvm_pmu *pmu,
> > + struct msr_data *msr_info)
> > +{
> > + u64 guest_debugctl, freeze_lbr_bits =
> DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |
> > +
> +static void intel_pmu_get_global_status(struct kvm_pmu *pmu,
> + struct msr_data *msr_info)
> +{
> + u64 guest_debugctl, freeze_lbr_bits = DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |
> + DEBUGCTLMSR_LBR;
> +
> + if
Arch v4 supports streamlined Freeze_LBR_on_PMI, so we set the
GLOBAL_STATUS_LBRS_FROZEN bit when the guest reads the global
status msr with freezing lbr in use.
Signed-off-by: Wei Wang
Cc: Paolo Bonzini
Cc: Andi Kleen
---
arch/x86/kvm/vmx/pmu_intel.c | 21 -
1 file
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