utland ; vivek.gau...@codeaurora.org
>> Cc: Michal Simek ; v.anuragku...@gmail.com; sundeep
>> subbaraya ; Ajay Yugalkishore Pandey
>> ; linux-kernel@vger.kernel.org; linux-arm-
>> ker...@lists.infradead.org; devicet...@vger.kernel.org
>> Subject: Re: [PATCH v5 2/2] p
>subbaraya ; Ajay Yugalkishore Pandey
>; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org
>Subject: Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy
>core
>
>Hi Anurag,
>
>On 17/01/19 9:39
g; Mark
>> Rutland ; vivek.gau...@codeaurora.org
>> Cc: Michal Simek ; v.anuragku...@gmail.com; sundeep
>> subbaraya ; Ajay Yugalkishore Pandey
>> ; linux-kernel@vger.kernel.org; linux-arm-
>> ker...@lists.infradead.org; devicet...@vger.kernel.org
>> Subject: Re: [PATCH
>subbaraya ; Ajay Yugalkishore Pandey
>; linux-kernel@vger.kernel.org; linux-arm-
>ker...@lists.infradead.org; devicet...@vger.kernel.org
>Subject: Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy
>core
>
>Hi,
>
>On 18/12/18 7:15 PM, Anurag Kum
Hi,
On 18/12/18 7:15 PM, Anurag Kumar Vulisha wrote:
> ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
> peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
> rely on any of the four GT lanes for PHY layer. This patch adds driver
> for that ZynqMP GT
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
rely on any of the four GT lanes for PHY layer. This patch adds driver
for that ZynqMP GT core.
Signed-off-by: Anurag Kumar Vulisha
---
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