Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

2019-02-06 Thread Kishon Vijay Abraham I
utland ; vivek.gau...@codeaurora.org >> Cc: Michal Simek ; v.anuragku...@gmail.com; sundeep >> subbaraya ; Ajay Yugalkishore Pandey >> ; linux-kernel@vger.kernel.org; linux-arm- >> ker...@lists.infradead.org; devicet...@vger.kernel.org >> Subject: Re: [PATCH v5 2/2] p

RE: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

2019-01-23 Thread Anurag Kumar Vulisha
>subbaraya ; Ajay Yugalkishore Pandey >; linux-kernel@vger.kernel.org; linux-arm- >ker...@lists.infradead.org; devicet...@vger.kernel.org >Subject: Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy >core > >Hi Anurag, > >On 17/01/19 9:39

Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

2019-01-21 Thread Kishon Vijay Abraham I
g; Mark >> Rutland ; vivek.gau...@codeaurora.org >> Cc: Michal Simek ; v.anuragku...@gmail.com; sundeep >> subbaraya ; Ajay Yugalkishore Pandey >> ; linux-kernel@vger.kernel.org; linux-arm- >> ker...@lists.infradead.org; devicet...@vger.kernel.org >> Subject: Re: [PATCH

RE: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

2019-01-17 Thread Anurag Kumar Vulisha
>subbaraya ; Ajay Yugalkishore Pandey >; linux-kernel@vger.kernel.org; linux-arm- >ker...@lists.infradead.org; devicet...@vger.kernel.org >Subject: Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy >core > >Hi, > >On 18/12/18 7:15 PM, Anurag Kum

Re: [PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

2019-01-16 Thread Kishon Vijay Abraham I
Hi, On 18/12/18 7:15 PM, Anurag Kumar Vulisha wrote: > ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed > peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can > rely on any of the four GT lanes for PHY layer. This patch adds driver > for that ZynqMP GT

[PATCH v5 2/2] phy: zynqmp: Add phy driver for xilinx zynqmp phy core

2018-12-18 Thread Anurag Kumar Vulisha
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha --- Changes in v5: