[PATCH v5 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-04-01 Thread Purna Chandra Mandal
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.

Signed-off-by: Purna Chandra Mandal 


---

Changes in v5:
- report error for unsupported bits_per_word.
- drop custom debugging messages in favor of core provided one.
- use if-else instead of 'goto'
- moved enable/disable of controller to prepare/unprepare_hardware()
- refactor setup(), just retain cs-deselect logic in setup()
  and apply the other setting in prepare_message().

Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments.

Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.

Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
  GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.

 drivers/spi/Kconfig |   6 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-pic32.c | 888 
 3 files changed, 895 insertions(+)
 create mode 100644 drivers/spi/spi-pic32.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
  This enables using the SPI master controller on the Orion chips.
 
+config SPI_PIC32
+   tristate "Microchip PIC32 series SPI"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for Microchip PIC32 SPI master controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K)   += spi-omap-100k.o
 obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..f8313ea
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,888 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SPI controller registers */
+struct pic32_spi_regs {
+   u32 ctrl;
+   u32 ctrl_clr;
+   u32 ctrl_set;
+   u32 ctrl_inv;
+   u32 status;
+   u32 status_clr;
+   u32 status_set;
+   u32 status_inv;
+   u32 buf;
+   u32 dontuse[3];
+   u32 baud;
+   u32 dontuse2[3];
+   u32 ctrl2;
+   u32 ctrl2_clr;
+   u32 ctrl2_set;
+   u32 ctrl2_inv;
+};
+
+/* Bit fields of SPI Control Register */
+#define CTRL_RX_INT_SHIFT  0  /* Rx interrupt generation */
+#define  RX_FIFO_EMTPY 0
+#define  RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define  RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define  RX_FIFO_FULL  3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT  2  /* TX interrupt generation */
+#define  TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define  TX_FIFO_EMTPY 1 /* empty */
+#define  TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define  

[PATCH v5 2/2] spi: spi-pic32: Add PIC32 SPI master driver

2016-04-01 Thread Purna Chandra Mandal
The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.

Signed-off-by: Purna Chandra Mandal 


---

Changes in v5:
- report error for unsupported bits_per_word.
- drop custom debugging messages in favor of core provided one.
- use if-else instead of 'goto'
- moved enable/disable of controller to prepare/unprepare_hardware()
- refactor setup(), just retain cs-deselect logic in setup()
  and apply the other setting in prepare_message().

Changes in v4:
- report error and bailout in case of missing irq(s).
- remove fallback to PIO mode in case of failure in DMA transfer.
- remove polling based PIO completely.
- drop spinlock
- update error message and comments.

Changes in v3:
- drop 'owner' field in driver struct.
- fix compilation warning in dma_addr_t print.

Changes in v2:
- drop internal function drain_rx_fifo()
- merge wrapper functions with callers wherever applicable
- sort includes alphabetically
- Kconfig: sort SPI_PIC32 alphabetically and add || COMPILE_TEST
- Makefile: sort SPI_PIC32 alphabetically
- replace cpu_relax() with ndelay() in disable_chip()
- drop spi controller driven /CS management completely, use only
  GPIO controller /CS.
- rename function names starting with 'spi' to avoid namespace conflict
- use .one_transfer() callback instead of .one_message().
- drop /CS assert-deassert functions as core provides those.
- fix race while completing transfer before disabling interrupt.

 drivers/spi/Kconfig |   6 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-pic32.c | 888 
 3 files changed, 895 insertions(+)
 create mode 100644 drivers/spi/spi-pic32.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7706416..22f973f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -396,6 +396,12 @@ config SPI_ORION
help
  This enables using the SPI master controller on the Orion chips.
 
+config SPI_PIC32
+   tristate "Microchip PIC32 series SPI"
+   depends on MACH_PIC32 || COMPILE_TEST
+   help
+ SPI driver for Microchip PIC32 SPI master controller.
+
 config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 8991ffc..1bcb417 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_OMAP_100K)   += spi-omap-100k.o
 obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
 obj-$(CONFIG_SPI_TI_QSPI)  += spi-ti-qspi.o
 obj-$(CONFIG_SPI_ORION)+= spi-orion.o
+obj-$(CONFIG_SPI_PIC32)+= spi-pic32.o
 obj-$(CONFIG_SPI_PL022)+= spi-pl022.o
 obj-$(CONFIG_SPI_PPC4xx)   += spi-ppc4xx.o
 spi-pxa2xx-platform-objs   := spi-pxa2xx.o
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
new file mode 100644
index 000..f8313ea
--- /dev/null
+++ b/drivers/spi/spi-pic32.c
@@ -0,0 +1,888 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Purna Chandra Mandal 
+ * Copyright (c) 2016, Microchip Technology Inc.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* SPI controller registers */
+struct pic32_spi_regs {
+   u32 ctrl;
+   u32 ctrl_clr;
+   u32 ctrl_set;
+   u32 ctrl_inv;
+   u32 status;
+   u32 status_clr;
+   u32 status_set;
+   u32 status_inv;
+   u32 buf;
+   u32 dontuse[3];
+   u32 baud;
+   u32 dontuse2[3];
+   u32 ctrl2;
+   u32 ctrl2_clr;
+   u32 ctrl2_set;
+   u32 ctrl2_inv;
+};
+
+/* Bit fields of SPI Control Register */
+#define CTRL_RX_INT_SHIFT  0  /* Rx interrupt generation */
+#define  RX_FIFO_EMTPY 0
+#define  RX_FIFO_NOT_EMPTY 1 /* not empty */
+#define  RX_FIFO_HALF_FULL 2 /* full by half or more */
+#define  RX_FIFO_FULL  3 /* completely full */
+
+#define CTRL_TX_INT_SHIFT  2  /* TX interrupt generation */
+#define  TX_FIFO_ALL_EMPTY 0 /* completely empty */
+#define  TX_FIFO_EMTPY 1 /* empty */
+#define  TX_FIFO_HALF_EMPTY2 /* empty by half or more */
+#define  TX_FIFO_NOT_FULL  3 /* atleast one empty */
+
+#define