Re: [PATCH v5 3/5] drivers/soc/litex: add LiteX SoC Controller driver

2020-05-07 Thread Mateusz Holenko
On Wed, Apr 29, 2020 at 5:12 AM Benjamin Herrenschmidt wrote: > > On Sat, 2020-04-25 at 13:42 +0200, Mateusz Holenko wrote: > > From: Pawel Czarnecki > > > > This commit adds driver for the FPGA-based LiteX SoC > > Controller from LiteX SoC builder. > > Sorry for jumping in late, Joel only just

Re: [PATCH v5 3/5] drivers/soc/litex: add LiteX SoC Controller driver

2020-04-29 Thread Gabriel L. Somlo
Hi Ben, On Wed, Apr 29, 2020 at 01:21:11PM +1000, Benjamin Herrenschmidt wrote: > On Mon, 2020-04-27 at 11:13 +0200, Mateusz Holenko wrote: > > As Gabriel Somlo suggested to me, I could still use > > readl/writel/ioread/iowrite() standard functions providing memory > > barriers *and* have values

Re: [PATCH v5 3/5] drivers/soc/litex: add LiteX SoC Controller driver

2020-04-28 Thread Benjamin Herrenschmidt
On Mon, 2020-04-27 at 11:13 +0200, Mateusz Holenko wrote: > As Gabriel Somlo suggested to me, I could still use > readl/writel/ioread/iowrite() standard functions providing memory > barriers *and* have values in CPU native endianness by using the > following constructs: > >

Re: [PATCH v5 3/5] drivers/soc/litex: add LiteX SoC Controller driver

2020-04-28 Thread Benjamin Herrenschmidt
On Sat, 2020-04-25 at 13:42 +0200, Mateusz Holenko wrote: > From: Pawel Czarnecki > > This commit adds driver for the FPGA-based LiteX SoC > Controller from LiteX SoC builder. Sorry for jumping in late, Joel only just pointed me to this :) > + * The purpose of `litex_set_reg`/`litex_get_reg`