> >> struct arm_pmu {
> >> @@ -117,6 +125,10 @@ struct arm_pmu {
> >> struct platform_device *plat_device;
> >> struct pmu_hw_events__percpu *hw_events;
> >> struct notifier_block hotplug_nb;
> >> +#ifdef CONFIG_SMP
> >> + int
On 31/03/15 17:20, Will Deacon wrote:
Hi Daniel,
On Wed, Mar 04, 2015 at 01:25:45PM +, Daniel Thompson wrote:
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and
On 31/03/15 18:08, Mark Rutland wrote:
Hi Daniel,
I'd very much like to see us converge on a solution for this soon. The
existing hack is getting in the way of other rework of the arm/arm64
perf code.
I'd quite like to see this patch sorted out too (mostly because one o my
"go to" devices
On 31/03/15 18:08, Mark Rutland wrote:
Hi Daniel,
I'd very much like to see us converge on a solution for this soon. The
existing hack is getting in the way of other rework of the arm/arm64
perf code.
I'd quite like to see this patch sorted out too (mostly because one o my
go to devices
On 31/03/15 17:20, Will Deacon wrote:
Hi Daniel,
On Wed, Mar 04, 2015 at 01:25:45PM +, Daniel Thompson wrote:
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and
struct arm_pmu {
@@ -117,6 +125,10 @@ struct arm_pmu {
struct platform_device *plat_device;
struct pmu_hw_events__percpu *hw_events;
struct notifier_block hotplug_nb;
+#ifdef CONFIG_SMP
+ int muxed_spi_workaround_irq;
Hi Daniel,
I'd very much like to see us converge on a solution for this soon. The
existing hack is getting in the way of other rework of the arm/arm64
perf code.
I think the approach this patch takes should work, but there are some
parts that can be cleaned up (hopefully mostly cosmetic).
Hi Daniel,
On Wed, Mar 04, 2015 at 01:25:45PM +, Daniel Thompson wrote:
> Some ARM platforms mux the PMU interrupt of every core into a single
> SPI. On such platforms if the PMU of any core except 0 raises an interrupt
> then it cannot be serviced and eventually, if you are lucky, the
Hi Daniel,
I'd very much like to see us converge on a solution for this soon. The
existing hack is getting in the way of other rework of the arm/arm64
perf code.
I think the approach this patch takes should work, but there are some
parts that can be cleaned up (hopefully mostly cosmetic).
Hi Daniel,
On Wed, Mar 04, 2015 at 01:25:45PM +, Daniel Thompson wrote:
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
irq detection might forcefully disable the interrupt.
On these SoCs it is not
Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and eventually, if you are lucky, the spurious
irq detection might forcefully disable the interrupt.
On these SoCs it is not
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