Re: [PATCH v6] mmc: sdhci-moxart: Add MOXA ART SDHCI driver
On Friday 17 January 2014, Jonas Jensen wrote: > Add SDHCI driver for MOXA ART SoCs. > > Signed-off-by: Jonas Jensen I think this should be renamed to something other than SDHCI, since that implies a specific register layout and would use the sdhci.c driver. Maybe moxart-mmc? > diff --git a/Documentation/devicetree/bindings/mmc/moxa,moxart-sdhci.txt > b/Documentation/devicetree/bindings/mmc/moxa,moxart-sdhci.txt > new file mode 100644 > index 000..020b13e > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/moxa,moxart-sdhci.txt > @@ -0,0 +1,28 @@ > +MOXA ART SD Host Controller Interface > + > +Required properties: > + > +- compatible : Must be "moxa,moxart-sdhci" > +- reg : Should contain registers location and length > +- interrupts : Should contain the interrupt number > +- clocks : Should contain phandle for the clock feeding the SDHCI > controller > + > +Optional properties: > + > +These are optional but required to enable DMA transfer mode: > + > +- dmas : Should contain two DMA channels, line request number must be 5 > for > + both channels > +- dma-names :Must be "tx", "rx" I think you should add a reference to bindings/mmc/mmc.txt here. > +#define MSD_CMD_REG 0 > +#define MSD_ARG_REG 4 > +#define MSD_RESP0_REG8 > +#define MSD_RESP1_REG0x0c > +#define MSD_RESP2_REG0x10 > +#define MSD_RESP3_REG0x14 > +#define MSD_RESP_CMD_REG 0x18 > +#define MSD_DATA_CTRL_REG0x1c > +#define MSD_DATA_TIMER_REG 0x20 > +#define MSD_DATA_LEN_REG 0x24 > +#define MSD_STATUS_REG 0x28 > +#define MSD_CLEAR_REG0x2c > +#define MSD_INT_MASK_REG 0x30 > +#define MSD_POWER_CTRL_REG 0x34 > +#define MSD_CLOCK_CTRL_REG 0x38 > +#define MSD_BUS_WIDTH_REG0x3c > +#define MSD_DATA_WIN_REG 0x40 > +#define MSD_FEATURE_REG 0x44 > +#define MSD_REVISION_REG 0x48 > + > +#define MMC_RSP_SHORT1 > +#define MMC_RSP_LONG 2 > +#define MMC_RSP_MASK 3 > +#define MMC_ERR_NONE 0 > +#define MMC_ERR_TIMEOUT 1 > +#define MMC_MODE_MMC 0 > +#define MMC_MODE_SD 1 > +#define MMC_ERR_BADCRC 2 > +#define MMC_VDD_360 23 > + > +#define MSD_RETRY_COUNT 10 > + > +#define REG_COMMAND 0 > +#define REG_ARGUMENT 4 > +#define REG_RESPONSE08 > +#define REG_RESPONSE112 > +#define REG_RESPONSE216 > +#define REG_RESPONSE320 > +#define REG_RESPONSE_COMMAND 24 > +#define REG_DATA_CONTROL 28 > +#define REG_DATA_TIMER 32 > +#define REG_DATA_LENGTH 36 > +#define REG_STATUS 40 > +#define REG_CLEAR44 > +#define REG_INTERRUPT_MASK 48 > +#define REG_POWER_CONTROL52 > +#define REG_CLOCK_CONTROL56 > +#define REG_BUS_WIDTH60 > +#define REG_DATA_WINDOW 64 > +#define REG_FEATURE 68 > +#define REG_REVISION 72 The lists seem duplicated here, there is an MSD_foo_REG for each REG_foo. > + /* > + * hardware does not support MMC_CAP_SD_HIGHSPEED > + * CMD6 will timeout and make things not work > + */ > + mmc->caps = MMC_CAP_4_BIT_DATA; Better get the bus-width from DT by calling the mmc_of_parse function. Some boards might connect only one data bit, or in fact 8 if it's an eMMC. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6] mmc: sdhci-moxart: Add MOXA ART SDHCI driver
Add SDHCI driver for MOXA ART SoCs. Signed-off-by: Jonas Jensen --- Notes: Changes in v6 fixes a kernel panic in moxart_dma_complete(). Panic only happens with CONFIG_SLAB or CONFIG_SLOB, the same code works for CONFIG_SLUB, and happens because a cookie belonging to the channel is passed to dmaengine_tx_status(), e.g. "host->tx_desc->chan->cookie". Panic log: [4.13] mmc0: new SD card at address e624 [4.17] nf_conntrack version 0.5.0 (357 buckets, 1428 max) [4.19] ip_tables: (C) 2000-2006 Netfilter Core Team [4.19] TCP: cubic registered [4.20] NET: Registered protocol family 10 [4.24] sit: IPv6 over IPv4 tunneling driver [4.27] mmcblk0: mmc0:e624 SD02G 1.84 GiB [4.32] mmcblk0: p1 [4.37] NET: Registered protocol family 17 [4.44] console [netcon0] enabled [4.44] netconsole: network logging started [4.45] moxart-rtc rtc.0: setting system clock to 2014-01-16 13:39:54 UTC (1389879594) [4.55] kjournald starting. Commit interval 5 seconds [4.55] EXT3-fs (mmcblk0p1): warning: maximal mount count reached, running e2fsck is recommended [4.57] EXT3-fs (mmcblk0p1): using internal journal [4.58] EXT3-fs (mmcblk0p1): mounted filesystem with ordered data mode [4.59] VFS: Mounted root (ext3 filesystem) on device 179:1. [4.61] devtmpfs: mounted [4.63] Freeing unused kernel memory: 156K (c0339000 - c036) [4.64] Unable to handle kernel paging request at virtual address [4.64] pgd = c0004000 [4.64] [] *pgd= [4.64] Internal error: Oops: 1 [#1] ARM [4.64] CPU: 0 PID: 0 Comm: swapper Not tainted 3.13.0-rc8-next-20140115+ #1577 [4.64] task: c03676a8 ti: c0362000 task.ti: c0362000 [4.64] PC is at moxart_dma_complete+0x14/0x68 [4.64] LR is at vchan_complete+0xcc/0xf4 [4.64] pc : []lr : []psr: a013 [4.64] sp : c0363e98 ip : c037ffcc fp : c0380f00 [4.64] r10: c1a867e0 r9 : c0380f38 r8 : c0363eb0 [4.64] r7 : 00100100 r6 : 00200200 r5 : c01a6710 r4 : c1a867e0 [4.64] r3 : c1ac0030 r2 : c0363e9c r1 : c03676a8 r0 : [4.64] Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel [4.64] Control: 397f Table: 4000 DAC: 0017 [4.64] Process swapper (pid: 0, stack limit = 0xc03621c0) [4.64] Stack: (0xc0363e98 to 0xc0364000) [4.64] 3e80: c1a867e0 c03676a8 [4.64] 3ea0: c03676a8 c1871158 c0154a28 c0363eb0 c0363eb0 6013 c1871184 [4.64] 3ec0: c03694d4 0006 0100 c0018fc4 c036bc60 0007 [4.64] 3ee0: 0040 c0362000 c0380f20 c0018950 c185b894 c185b894 c185b840 0006 [4.64] 3f00: 000a 0020 0001 8ca1 0011 c0934d40 [4.64] 3f20: 0001 c0363f68 66015261 c0352624 c0018d38 0011 c0009a14 [4.64] 3f40: c18020e4 0100 0018 c0008538 c0009b94 2013 c0363f9c [4.64] 3f60: c0998200 c000bfb8 0001 c03676a8 2013 c0362000 c0364020 [4.64] 3f80: c0364110 c0998200 66015261 c0352624 f6aa4ecf c0363fb0 [4.64] 3fa0: c003da20 c0009b94 2013 c03676a8 c0047548 c03676a8 c0339988 [4.64] 3fc0: c03394d4 c0352624 397d [4.64] 3fe0: c03640a4 c0352620 c03689ec 4000 003517b4 8040 [4.64] [] (moxart_dma_complete) from [] (vchan_complete+0xcc/0xf4) [4.64] [] (vchan_complete) from [] (tasklet_action+0x84/0xd4) [4.64] [] (tasklet_action) from [] (__do_softirq+0x170/0x2a4) [4.64] [] (__do_softirq) from [] (irq_exit+0x80/0x100) [4.64] [] (irq_exit) from [] (handle_IRQ+0x60/0x80) [4.64] [] (handle_IRQ) from [] (handle_irq+0x88/0x9c) [4.64] [] (handle_irq) from [] (__irq_svc+0x38/0x48) [4.64] Exception stack(0xc0363f68 to 0xc0363fb0) [4.64] 3f60: 0001 c03676a8 2013 c0362000 c0364020 [4.64] 3f80: c0364110 c0998200 66015261 c0352624 f6aa4ecf c0363fb0 [4.64] 3fa0: c003da20 c0009b94 2013 [4.64] [] (__irq_svc) from [] (arch_cpu_idle+0x3c/0x48) [4.64] [] (arch_cpu_idle) from [] (cpu_startup_entry+0x80/0xf0) [4.64] [] (cpu_startup_entry) from [] (start_kernel+0x298/0x2e0) [4.64] Code: e5903030 e1a04000 e593000c e28d2004 (e5903000) [4.95] ---[ end
[PATCH v6] mmc: sdhci-moxart: Add MOXA ART SDHCI driver
Add SDHCI driver for MOXA ART SoCs. Signed-off-by: Jonas Jensen jonas.jen...@gmail.com --- Notes: Changes in v6 fixes a kernel panic in moxart_dma_complete(). Panic only happens with CONFIG_SLAB or CONFIG_SLOB, the same code works for CONFIG_SLUB, and happens because a cookie belonging to the channel is passed to dmaengine_tx_status(), e.g. host-tx_desc-chan-cookie. Panic log: [4.13] mmc0: new SD card at address e624 [4.17] nf_conntrack version 0.5.0 (357 buckets, 1428 max) [4.19] ip_tables: (C) 2000-2006 Netfilter Core Team [4.19] TCP: cubic registered [4.20] NET: Registered protocol family 10 [4.24] sit: IPv6 over IPv4 tunneling driver [4.27] mmcblk0: mmc0:e624 SD02G 1.84 GiB [4.32] mmcblk0: p1 [4.37] NET: Registered protocol family 17 [4.44] console [netcon0] enabled [4.44] netconsole: network logging started [4.45] moxart-rtc rtc.0: setting system clock to 2014-01-16 13:39:54 UTC (1389879594) [4.55] kjournald starting. Commit interval 5 seconds [4.55] EXT3-fs (mmcblk0p1): warning: maximal mount count reached, running e2fsck is recommended [4.57] EXT3-fs (mmcblk0p1): using internal journal [4.58] EXT3-fs (mmcblk0p1): mounted filesystem with ordered data mode [4.59] VFS: Mounted root (ext3 filesystem) on device 179:1. [4.61] devtmpfs: mounted [4.63] Freeing unused kernel memory: 156K (c0339000 - c036) [4.64] Unable to handle kernel paging request at virtual address [4.64] pgd = c0004000 [4.64] [] *pgd= [4.64] Internal error: Oops: 1 [#1] ARM [4.64] CPU: 0 PID: 0 Comm: swapper Not tainted 3.13.0-rc8-next-20140115+ #1577 [4.64] task: c03676a8 ti: c0362000 task.ti: c0362000 [4.64] PC is at moxart_dma_complete+0x14/0x68 [4.64] LR is at vchan_complete+0xcc/0xf4 [4.64] pc : [c01a6724]lr : [c0154a28]psr: a013 [4.64] sp : c0363e98 ip : c037ffcc fp : c0380f00 [4.64] r10: c1a867e0 r9 : c0380f38 r8 : c0363eb0 [4.64] r7 : 00100100 r6 : 00200200 r5 : c01a6710 r4 : c1a867e0 [4.64] r3 : c1ac0030 r2 : c0363e9c r1 : c03676a8 r0 : [4.64] Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel [4.64] Control: 397f Table: 4000 DAC: 0017 [4.64] Process swapper (pid: 0, stack limit = 0xc03621c0) [4.64] Stack: (0xc0363e98 to 0xc0364000) [4.64] 3e80: c1a867e0 c03676a8 [4.64] 3ea0: c03676a8 c1871158 c0154a28 c0363eb0 c0363eb0 6013 c1871184 [4.64] 3ec0: c03694d4 0006 0100 c0018fc4 c036bc60 0007 [4.64] 3ee0: 0040 c0362000 c0380f20 c0018950 c185b894 c185b894 c185b840 0006 [4.64] 3f00: 000a 0020 0001 8ca1 0011 c0934d40 [4.64] 3f20: 0001 c0363f68 66015261 c0352624 c0018d38 0011 c0009a14 [4.64] 3f40: c18020e4 0100 0018 c0008538 c0009b94 2013 c0363f9c [4.64] 3f60: c0998200 c000bfb8 0001 c03676a8 2013 c0362000 c0364020 [4.64] 3f80: c0364110 c0998200 66015261 c0352624 f6aa4ecf c0363fb0 [4.64] 3fa0: c003da20 c0009b94 2013 c03676a8 c0047548 c03676a8 c0339988 [4.64] 3fc0: c03394d4 c0352624 397d [4.64] 3fe0: c03640a4 c0352620 c03689ec 4000 003517b4 8040 [4.64] [c01a6724] (moxart_dma_complete) from [c0154a28] (vchan_complete+0xcc/0xf4) [4.64] [c0154a28] (vchan_complete) from [c0018fc4] (tasklet_action+0x84/0xd4) [4.64] [c0018fc4] (tasklet_action) from [c0018950] (__do_softirq+0x170/0x2a4) [4.64] [c0018950] (__do_softirq) from [c0018d38] (irq_exit+0x80/0x100) [4.64] [c0018d38] (irq_exit) from [c0009a14] (handle_IRQ+0x60/0x80) [4.64] [c0009a14] (handle_IRQ) from [c0008538] (handle_irq+0x88/0x9c) [4.64] [c0008538] (handle_irq) from [c000bfb8] (__irq_svc+0x38/0x48) [4.64] Exception stack(0xc0363f68 to 0xc0363fb0) [4.64] 3f60: 0001 c03676a8 2013 c0362000 c0364020 [4.64] 3f80: c0364110 c0998200 66015261 c0352624 f6aa4ecf c0363fb0 [4.64] 3fa0: c003da20 c0009b94 2013 [4.64] [c000bfb8] (__irq_svc) from [c0009b94] (arch_cpu_idle+0x3c/0x48) [4.64] [c0009b94] (arch_cpu_idle) from [c0047548] (cpu_startup_entry+0x80/0xf0)
Re: [PATCH v6] mmc: sdhci-moxart: Add MOXA ART SDHCI driver
On Friday 17 January 2014, Jonas Jensen wrote: Add SDHCI driver for MOXA ART SoCs. Signed-off-by: Jonas Jensen jonas.jen...@gmail.com I think this should be renamed to something other than SDHCI, since that implies a specific register layout and would use the sdhci.c driver. Maybe moxart-mmc? diff --git a/Documentation/devicetree/bindings/mmc/moxa,moxart-sdhci.txt b/Documentation/devicetree/bindings/mmc/moxa,moxart-sdhci.txt new file mode 100644 index 000..020b13e --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/moxa,moxart-sdhci.txt @@ -0,0 +1,28 @@ +MOXA ART SD Host Controller Interface + +Required properties: + +- compatible : Must be moxa,moxart-sdhci +- reg : Should contain registers location and length +- interrupts : Should contain the interrupt number +- clocks : Should contain phandle for the clock feeding the SDHCI controller + +Optional properties: + +These are optional but required to enable DMA transfer mode: + +- dmas : Should contain two DMA channels, line request number must be 5 for + both channels +- dma-names :Must be tx, rx I think you should add a reference to bindings/mmc/mmc.txt here. +#define MSD_CMD_REG 0 +#define MSD_ARG_REG 4 +#define MSD_RESP0_REG8 +#define MSD_RESP1_REG0x0c +#define MSD_RESP2_REG0x10 +#define MSD_RESP3_REG0x14 +#define MSD_RESP_CMD_REG 0x18 +#define MSD_DATA_CTRL_REG0x1c +#define MSD_DATA_TIMER_REG 0x20 +#define MSD_DATA_LEN_REG 0x24 +#define MSD_STATUS_REG 0x28 +#define MSD_CLEAR_REG0x2c +#define MSD_INT_MASK_REG 0x30 +#define MSD_POWER_CTRL_REG 0x34 +#define MSD_CLOCK_CTRL_REG 0x38 +#define MSD_BUS_WIDTH_REG0x3c +#define MSD_DATA_WIN_REG 0x40 +#define MSD_FEATURE_REG 0x44 +#define MSD_REVISION_REG 0x48 + +#define MMC_RSP_SHORT1 +#define MMC_RSP_LONG 2 +#define MMC_RSP_MASK 3 +#define MMC_ERR_NONE 0 +#define MMC_ERR_TIMEOUT 1 +#define MMC_MODE_MMC 0 +#define MMC_MODE_SD 1 +#define MMC_ERR_BADCRC 2 +#define MMC_VDD_360 23 + +#define MSD_RETRY_COUNT 10 + +#define REG_COMMAND 0 +#define REG_ARGUMENT 4 +#define REG_RESPONSE08 +#define REG_RESPONSE112 +#define REG_RESPONSE216 +#define REG_RESPONSE320 +#define REG_RESPONSE_COMMAND 24 +#define REG_DATA_CONTROL 28 +#define REG_DATA_TIMER 32 +#define REG_DATA_LENGTH 36 +#define REG_STATUS 40 +#define REG_CLEAR44 +#define REG_INTERRUPT_MASK 48 +#define REG_POWER_CONTROL52 +#define REG_CLOCK_CONTROL56 +#define REG_BUS_WIDTH60 +#define REG_DATA_WINDOW 64 +#define REG_FEATURE 68 +#define REG_REVISION 72 The lists seem duplicated here, there is an MSD_foo_REG for each REG_foo. + /* + * hardware does not support MMC_CAP_SD_HIGHSPEED + * CMD6 will timeout and make things not work + */ + mmc-caps = MMC_CAP_4_BIT_DATA; Better get the bus-width from DT by calling the mmc_of_parse function. Some boards might connect only one data bit, or in fact 8 if it's an eMMC. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
