[PATCH v6 0/3] powerpc: powernv: Fastsleep workaround behavior

2015-04-19 Thread Shreyas B. Prabhu
Fastsleep is one of the idle state which cpuidle subsystem currently uses on power8 machines. In this state L2 cache is brought down to a threshold voltage. Therefore when the core is in fastsleep, the communication between L2 and L3 needs to be fenced. But there is a bug in the current power8

[PATCH v6 0/3] powerpc: powernv: Fastsleep workaround behavior

2015-04-19 Thread Shreyas B. Prabhu
Fastsleep is one of the idle state which cpuidle subsystem currently uses on power8 machines. In this state L2 cache is brought down to a threshold voltage. Therefore when the core is in fastsleep, the communication between L2 and L3 needs to be fenced. But there is a bug in the current power8