Re: [PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number

2018-09-10 Thread Pu Wen
On 2018/9/11 2:06, Borislav Petkov wrote: On Mon, Sep 10, 2018 at 09:16:03PM +0800, Pu Wen wrote: The Hygon Dhyana CPU have a special magic MSR way to force WB for From the last review round: Also, it is "The ... CPU has a special..." Please take your time and incorporate *all* review feedb

Re: [PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number

2018-09-10 Thread Borislav Petkov
On Mon, Sep 10, 2018 at 09:16:03PM +0800, Pu Wen wrote: > The Hygon Dhyana CPU have a special magic MSR way to force WB for >From the last review round: Also, it is "The ... CPU has a special..." Please take your time and incorporate *all* review feedback - no need to *rush* a new revision out a

[PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number

2018-09-10 Thread Pu Wen
The Hygon Dhyana CPU have a special magic MSR way to force WB for memory >4GB, and support TOP_MEM2. Therefore, it is necessary to add Hygon Dhyana support in amd_special_default_mtrr(). The number of variable MTRRs for Hygon is 2 as AMD's. Signed-off-by: Pu Wen --- arch/x86/kernel/cpu/mtrr/cle