On 2018/9/20 1:20, Lendacky, Thomas wrote:
@@ -197,12 +212,25 @@ int amd_cache_northbridges(void)
u16 i = 0;
struct amd_northbridge *nb;
struct pci_dev *root, *misc, *link;
+ const struct pci_device_id *root_ids = NULL;
+ const struct pci_device_id *misc_ids =
On Wed, 19 Sep 2018, Lendacky, Thomas wrote:
>
> To be compatible with "before this patch" you should probably do:
>
> if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
> root_ids = hygon_root_ids;
> misc_ids = hygon_nb_misc_ids;
> link_ids = hygo
On 09/10/2018 08:17 AM, Pu Wen wrote:
> As Hygon registered its PCI Vendor ID as a new one 0x1d94, and there
> are PCI Devices 0x1450/0x1463/0x1464 for Host bridge on Hygon Dhyana
> platforms, so add Hygon Dhyana support to the PCI and north bridge
> subsystem by using the code path of AMD family 1
On Mon, Sep 10, 2018 at 09:17:11PM +0800, Pu Wen wrote:
> As Hygon registered its PCI Vendor ID as a new one 0x1d94, and there
> are PCI Devices 0x1450/0x1463/0x1464 for Host bridge on Hygon Dhyana
> platforms, so add Hygon Dhyana support to the PCI and north bridge
> subsystem by using the code pa
As Hygon registered its PCI Vendor ID as a new one 0x1d94, and there
are PCI Devices 0x1450/0x1463/0x1464 for Host bridge on Hygon Dhyana
platforms, so add Hygon Dhyana support to the PCI and north bridge
subsystem by using the code path of AMD family 17h.
Acked-by: Bjorn Helgaas# pci_ids.h
Si
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