On Wed, 19 Dec 2018, Li, Aubrey wrote:
> On 2018/12/19 5:38, Andi Kleen wrote:
> >> I misunderstood, you mean 32bit kernel, not 32bit machine. Theoretically
> >> 32bit
> >> kernel can use AVX512, but not sure if anyone use it like this.
> >> get_jiffies_64()
> >> includes jiffies_lock ops so not
On 2018/12/19 5:38, Andi Kleen wrote:
>> I misunderstood, you mean 32bit kernel, not 32bit machine. Theoretically
>> 32bit
>> kernel can use AVX512, but not sure if anyone use it like this.
>> get_jiffies_64()
>> includes jiffies_lock ops so not good in context switch. So I want to use raw
>>
On 2018/12/19 1:14, Dave Hansen wrote:
> On 12/18/18 7:32 AM, Thomas Gleixner wrote:
>> What exactly prevents a 32bit kernel from having the AVX512 feature bit
>> set? And if it cannot be set on 32bit, then why are you compiling that code
>> in at all?
>
> There are three different AVX-512 states
On Tue, Dec 18, 2018 at 01:44:41PM -0800, Dave Hansen wrote:
> On 12/18/18 1:38 PM, Andi Kleen wrote:
> >> I misunderstood, you mean 32bit kernel, not 32bit machine. Theoretically
> >> 32bit
> >> kernel can use AVX512, but not sure if anyone use it like this.
> >> get_jiffies_64()
> >> includes
On 12/18/18 1:38 PM, Andi Kleen wrote:
>> I misunderstood, you mean 32bit kernel, not 32bit machine. Theoretically
>> 32bit
>> kernel can use AVX512, but not sure if anyone use it like this.
>> get_jiffies_64()
>> includes jiffies_lock ops so not good in context switch. So I want to use raw
>>
> I misunderstood, you mean 32bit kernel, not 32bit machine. Theoretically 32bit
> kernel can use AVX512, but not sure if anyone use it like this.
> get_jiffies_64()
> includes jiffies_lock ops so not good in context switch. So I want to use raw
> jiffies_64 here. jiffies is a good candidate but
On 12/18/18 7:32 AM, Thomas Gleixner wrote:
> What exactly prevents a 32bit kernel from having the AVX512 feature bit
> set? And if it cannot be set on 32bit, then why are you compiling that code
> in at all?
There are three different AVX-512 states (and three bits) which Aubrey's
patch checks.
On 2018/12/18 23:32, Thomas Gleixner wrote:
> On Tue, 18 Dec 2018, Li, Aubrey wrote:
>
>> On 2018/12/18 22:14, Thomas Gleixner wrote:
>>> On Tue, 18 Dec 2018, Aubrey Li wrote:
diff --git a/arch/x86/include/asm/fpu/internal.h
b/arch/x86/include/asm/fpu/internal.h
index
On Tue, 18 Dec 2018, Li, Aubrey wrote:
> On 2018/12/18 22:14, Thomas Gleixner wrote:
> > On Tue, 18 Dec 2018, Aubrey Li wrote:
> >> diff --git a/arch/x86/include/asm/fpu/internal.h
> >> b/arch/x86/include/asm/fpu/internal.h
> >> index a38bf5a1e37a..8778ac172255 100644
> >> ---
On 2018/12/18 22:14, Thomas Gleixner wrote:
> On Tue, 18 Dec 2018, Aubrey Li wrote:
>> diff --git a/arch/x86/include/asm/fpu/internal.h
>> b/arch/x86/include/asm/fpu/internal.h
>> index a38bf5a1e37a..8778ac172255 100644
>> --- a/arch/x86/include/asm/fpu/internal.h
>> +++
On Tue, 18 Dec 2018, Aubrey Li wrote:
> diff --git a/arch/x86/include/asm/fpu/internal.h
> b/arch/x86/include/asm/fpu/internal.h
> index a38bf5a1e37a..8778ac172255 100644
> --- a/arch/x86/include/asm/fpu/internal.h
> +++ b/arch/x86/include/asm/fpu/internal.h
> @@ -411,6 +411,13 @@ static inline
User space tools which do automated task placement need information
about AVX-512 usage of tasks, because AVX-512 usage could cause core
turbo frequency drop and impact the running task on the sibling CPU.
The XSAVE hardware structure has bits that indicate when valid state
is present in
12 matches
Mail list logo
