Re: [PATCH v6 19/41] clk: davinci: New driver for TI DA8XX USB PHY clocks

On Saturday 20 January 2018 10:43 PM, David Lechner wrote: > diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h > index 54ea3ff..04b48b3 100644 > --- a/include/linux/clk/davinci.h > +++ b/include/linux/clk/davinci.h > @@ -9,6 +9,9 @@ > > #include > > +struct clk; >

Re: [PATCH v6 19/41] clk: davinci: New driver for TI DA8XX USB PHY clocks

On Saturday 20 January 2018 10:43 PM, David Lechner wrote: > diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h > index 54ea3ff..04b48b3 100644 > --- a/include/linux/clk/davinci.h > +++ b/include/linux/clk/davinci.h > @@ -9,6 +9,9 @@ > > #include > > +struct clk; >

[PATCH v6 19/41] clk: davinci: New driver for TI DA8XX USB PHY clocks

This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes

[PATCH v6 19/41] clk: davinci: New driver for TI DA8XX USB PHY clocks

This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes