Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-29 Thread Lorenzo Pieralisi
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote: On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote: The Krait L1/L2 error reporting hardware is made up a per-CPU interrupt for the L1 cache and a SPI interrupt for the L2. Cc: Lorenzo Pieralisi

Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-29 Thread Borislav Petkov
On Tue, Apr 29, 2014 at 11:34:00AM +0100, Lorenzo Pieralisi wrote: Sorry for the delay in replying. Those cache bindings need an ACK to get merged, and were introduced so that idle states can retrieve power domain information for caches. I am going to revive the idle bindings thread to see

Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-08 Thread Borislav Petkov
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote: The Krait L1/L2 error reporting hardware is made up a per-CPU interrupt for the L1 cache and a SPI interrupt for the L2. Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Kumar Gala

Re: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-08 Thread Stephen Boyd
On 04/08/14 08:39, Borislav Petkov wrote: On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote: The Krait L1/L2 error reporting hardware is made up a per-CPU interrupt for the L1 cache and a SPI interrupt for the L2. Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com Cc: Mark Rutland

[PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts

2014-04-04 Thread Stephen Boyd
The Krait L1/L2 error reporting hardware is made up a per-CPU interrupt for the L1 cache and a SPI interrupt for the L2. Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Kumar Gala ga...@codeaurora.org Cc: devicet...@vger.kernel.org Signed-off-by: Stephen