s (if I did the RVC math right) in order to save two. :)
> >
> > Paolo
> >
> >> +"li %[tscause], 0\n"
> >> +#ifdef CONFIG_64BIT
> >> +"ld %[val], (%[addr])\n"
> >> +#else
> >> +
Anup Patel
CC: Paul Walmsley
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CC: Atish Patra
CC: Alistair Francis
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CC: Christoph Hellwig
CC:
On Mon, Sep 23, 2019 at 7:03 PM Paolo Bonzini wrote:
>
> On 23/09/19 15:09, Anup Patel wrote:
> >>> +#ifndef CONFIG_RISCV_ISA_C
> >>> + "li %[tilen], 4\n"
> >>> +#else
> >>> + "li %[tilen], 2\n"
> >>> +#endif
> >>
> >> Can you use an assembler directive to
On 23/09/19 15:09, Anup Patel wrote:
>>> +#ifndef CONFIG_RISCV_ISA_C
>>> + "li %[tilen], 4\n"
>>> +#else
>>> + "li %[tilen], 2\n"
>>> +#endif
>>
>> Can you use an assembler directive to force using a non-compressed
>> format for ld and lw? This would get
On Mon, Sep 23, 2019 at 4:42 PM Paolo Bonzini wrote:
>
> On 04/09/19 18:15, Anup Patel wrote:
> > + unsigned long guest_sstatus =
> > + vcpu->arch.guest_context.sstatus | SR_MXR;
> > + unsigned long guest_hstatus =
> > +
On 04/09/19 18:15, Anup Patel wrote:
> + unsigned long guest_sstatus =
> + vcpu->arch.guest_context.sstatus | SR_MXR;
> + unsigned long guest_hstatus =
> + vcpu->arch.guest_context.hstatus | HSTATUS_SPRV;
> + unsigned long guest_vsstatus,
On 04.09.19 18:15, Anup Patel wrote:
We will get stage2 page faults whenever Guest/VM access SW emulated
MMIO device or unmapped Guest RAM.
This patch implements MMIO read/write emulation by extracting MMIO
details from the trapped load/store instruction and forwarding the
MMIO read/write to
We will get stage2 page faults whenever Guest/VM access SW emulated
MMIO device or unmapped Guest RAM.
This patch implements MMIO read/write emulation by extracting MMIO
details from the trapped load/store instruction and forwarding the
MMIO read/write to user-space. The actual MMIO emulation
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