On Tue, 28 Oct 2014, Dave Hansen wrote:
> On 10/24/2014 05:08 AM, Thomas Gleixner wrote:
> > On Sun, 12 Oct 2014, Qiaowei Ren wrote:
> >> + /*
> >> + * Go poke the address of the new bounds table in to the
> >> + * bounds directory entry out in userspace memory. Note:
> >> + * we may race
On 10/24/2014 05:08 AM, Thomas Gleixner wrote:
> On Sun, 12 Oct 2014, Qiaowei Ren wrote:
>> +/*
>> + * Go poke the address of the new bounds table in to the
>> + * bounds directory entry out in userspace memory. Note:
>> + * we may race with another CPU instantiating the same
On 10/24/2014 05:08 AM, Thomas Gleixner wrote:
On Sun, 12 Oct 2014, Qiaowei Ren wrote:
+/*
+ * Go poke the address of the new bounds table in to the
+ * bounds directory entry out in userspace memory. Note:
+ * we may race with another CPU instantiating the same table.
+
On Tue, 28 Oct 2014, Dave Hansen wrote:
On 10/24/2014 05:08 AM, Thomas Gleixner wrote:
On Sun, 12 Oct 2014, Qiaowei Ren wrote:
+ /*
+ * Go poke the address of the new bounds table in to the
+ * bounds directory entry out in userspace memory. Note:
+ * we may race with another
On 10/24/2014 08:08 PM, Thomas Gleixner wrote:
On Sun, 12 Oct 2014, Qiaowei Ren wrote:
+ /*
+* Go poke the address of the new bounds table in to the
+* bounds directory entry out in userspace memory. Note:
+* we may race with another CPU instantiating the same
On 10/24/2014 08:08 PM, Thomas Gleixner wrote:
On Sun, 12 Oct 2014, Qiaowei Ren wrote:
+ /*
+* Go poke the address of the new bounds table in to the
+* bounds directory entry out in userspace memory. Note:
+* we may race with another CPU instantiating the same
On Sun, 12 Oct 2014, Qiaowei Ren wrote:
> + /*
> + * Go poke the address of the new bounds table in to the
> + * bounds directory entry out in userspace memory. Note:
> + * we may race with another CPU instantiating the same table.
> + * In that case the cmpxchg will see
On Sun, 12 Oct 2014, Qiaowei Ren wrote:
+ /*
+ * Go poke the address of the new bounds table in to the
+ * bounds directory entry out in userspace memory. Note:
+ * we may race with another CPU instantiating the same table.
+ * In that case the cmpxchg will see an
MPX only has 4 hardware registers for storing bounds information.
If MPX-enabled code needs more than these 4 registers, it needs to
spill them somewhere. It has two special instructions for this
which allow the bounds to be moved between the bounds registers
and some new "bounds tables".
They
MPX only has 4 hardware registers for storing bounds information.
If MPX-enabled code needs more than these 4 registers, it needs to
spill them somewhere. It has two special instructions for this
which allow the bounds to be moved between the bounds registers
and some new bounds tables.
They are
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