> >>> + /* Initialize and clear the no dependency bits */
> >>> + vmx->pt_desc.ctl_bitmask = ~0ULL;
> >> This looks redundant, doesn't it?
> > This is a bit mask for RTIT_CTL MSR and it will make & with the value of
> > RTIT_CLT from guest.
> > The reserved bits will be 1 in this bit mask and the
On 08/06/2018 16:56, Kang, Luwei wrote:
>>> + /* Initialize and clear the no dependency bits */
>>> + vmx->pt_desc.ctl_bitmask = ~0ULL;
>> This looks redundant, doesn't it?
> This is a bit mask for RTIT_CTL MSR and it will make & with the value of
> RTIT_CLT from guest.
> The reserved bits wil
> On Tue, May 22, 2018 at 12:52:12PM +0800, Luwei Kang wrote:
> > Initialize the Intel PT configuration when cpuid update.
>
> Is it the CPUID configuration? Is it the MSR configuration? Is it both?
> Kind of looks like both. Not sure what is the cpuid update, though.
>
> > Include cpuid inforamt
On Tue, May 22, 2018 at 12:52:12PM +0800, Luwei Kang wrote:
> Initialize the Intel PT configuration when cpuid update.
Is it the CPUID configuration? Is it the MSR configuration? Is it both?
Kind of looks like both. Not sure what is the cpuid update, though.
> Include cpuid inforamtion, rtit_ctl
Initialize the Intel PT configuration when cpuid update.
Include cpuid inforamtion, rtit_ctl bit mask and the number of
address ranges.
Signed-off-by: Luwei Kang
---
arch/x86/kvm/vmx.c | 70 ++
1 file changed, 70 insertions(+)
diff --git a/arc
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