Re: [PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support

2017-11-03 Thread Suzuki K Poulose
On 03/11/17 12:20, Mark Rutland wrote: Hi Suzuki, This looks good, but there are a couple of edge cases I think that we need to handle, as noted below. On Tue, Oct 31, 2017 at 05:23:18PM +, Suzuki K Poulose wrote: Changes since V8: - Fill in the "module" field for the PMU to prevent

Re: [PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support

2017-11-03 Thread Suzuki K Poulose
On 03/11/17 12:20, Mark Rutland wrote: Hi Suzuki, This looks good, but there are a couple of edge cases I think that we need to handle, as noted below. On Tue, Oct 31, 2017 at 05:23:18PM +, Suzuki K Poulose wrote: Changes since V8: - Fill in the "module" field for the PMU to prevent

Re: [PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support

2017-11-03 Thread Mark Rutland
Hi Suzuki, This looks good, but there are a couple of edge cases I think that we need to handle, as noted below. On Tue, Oct 31, 2017 at 05:23:18PM +, Suzuki K Poulose wrote: > Changes since V8: > - Fill in the "module" field for the PMU to prevent the module unload >when the PMU is

Re: [PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support

2017-11-03 Thread Mark Rutland
Hi Suzuki, This looks good, but there are a couple of edge cases I think that we need to handle, as noted below. On Tue, Oct 31, 2017 at 05:23:18PM +, Suzuki K Poulose wrote: > Changes since V8: > - Fill in the "module" field for the PMU to prevent the module unload >when the PMU is

[PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support

2017-10-31 Thread Suzuki K Poulose
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster. The PMU allows counting the various events related to L3, SCU etc, along with providing a

[PATCH v9 8/8] perf: ARM DynamIQ Shared Unit PMU support

2017-10-31 Thread Suzuki K Poulose
Add support for the Cluster PMU part of the ARM DynamIQ Shared Unit (DSU). The DSU integrates one or more cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster. The PMU allows counting the various events related to L3, SCU etc, along with providing a