Yes I'm going to do a v3.
Regards,
Loic
On 23/09/2014 20:36, Westerberg, Mika wrote:
On Tue, Sep 23, 2014 at 05:44:43PM +0200, Linus Walleij wrote:
On Wed, Sep 17, 2014 at 3:47 PM, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io
Yes I'm going to do a v3.
Regards,
Loic
On 23/09/2014 20:36, Westerberg, Mika wrote:
On Tue, Sep 23, 2014 at 05:44:43PM +0200, Linus Walleij wrote:
On Wed, Sep 17, 2014 at 3:47 PM, Loic Poulain loic.poul...@intel.com wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has
On Tue, Sep 23, 2014 at 05:44:43PM +0200, Linus Walleij wrote:
> On Wed, Sep 17, 2014 at 3:47 PM, Loic Poulain wrote:
>
> > Direct Irq En bit can be initialized to a bad value.
> > This bit has to be cleared for io access mode.
> >
> > Signed-off-by: Loic Poulain
> > ---
> > v2: Apply over
On Wed, Sep 17, 2014 at 3:47 PM, Loic Poulain wrote:
> Direct Irq En bit can be initialized to a bad value.
> This bit has to be cleared for io access mode.
>
> Signed-off-by: Loic Poulain
> ---
> v2: Apply over ff998356b644ebe723127bd9eec6040b59a4a4f6 + add Warning
I can't figure out if the
On Wed, Sep 17, 2014 at 3:47 PM, Loic Poulain loic.poul...@intel.com wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io access mode.
Signed-off-by: Loic Poulain loic.poul...@intel.com
---
v2: Apply over ff998356b644ebe723127bd9eec6040b59a4a4f6 +
On Tue, Sep 23, 2014 at 05:44:43PM +0200, Linus Walleij wrote:
On Wed, Sep 17, 2014 at 3:47 PM, Loic Poulain loic.poul...@intel.com wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io access mode.
Signed-off-by: Loic Poulain
On 14-09-18 02:55 AM, Mika Westerberg wrote:
On Thu, Sep 18, 2014 at 11:41:13AM +0200, Samuel Ortiz wrote:
Hi Mika,
On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad
On Thu, Sep 18, 2014 at 11:41:13AM +0200, Samuel Ortiz wrote:
> Hi Mika,
>
> On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
> > On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
> > > Direct Irq En bit can be initialized to a bad value.
> > > This bit has to be
On Thu, Sep 18, 2014 at 11:31:35AM +0200, Loic Poulain wrote:
> Warn seems necessary because we unconditionally change
> the pin behavior, I didn't meet any case where direct irq is truly
> used on our platform. But maybe it could happen?
> Don't want to cause any hidden regression.
The datasheet
Hi Mika,
On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
> On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
> > Direct Irq En bit can be initialized to a bad value.
> > This bit has to be cleared for io access mode.
>
> +Eric
>
> I would like to have a bit better
Warn seems necessary because we unconditionally change
the pin behavior, I didn't meet any case where direct irq is truly
used on our platform. But maybe it could happen?
Don't want to cause any hidden regression.
Moreover if it is confirmed that is an hardware issue (BIOS),
We can just keep
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
> Direct Irq En bit can be initialized to a bad value.
> This bit has to be cleared for io access mode.
+Eric
I would like to have a bit better explanation *why* this bit needs to be
cleared.
Also want to ask Eric (who added the
On 14-09-18 02:55 AM, Mika Westerberg wrote:
On Thu, Sep 18, 2014 at 11:41:13AM +0200, Samuel Ortiz wrote:
Hi Mika,
On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io access mode.
+Eric
I would like to have a bit better explanation *why* this bit needs to be
cleared.
Also want to ask Eric (who added the
Warn seems necessary because we unconditionally change
the pin behavior, I didn't meet any case where direct irq is truly
used on our platform. But maybe it could happen?
Don't want to cause any hidden regression.
Moreover if it is confirmed that is an hardware issue (BIOS),
We can just keep
Hi Mika,
On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io access mode.
+Eric
I would like to have a bit better
On Thu, Sep 18, 2014 at 11:31:35AM +0200, Loic Poulain wrote:
Warn seems necessary because we unconditionally change
the pin behavior, I didn't meet any case where direct irq is truly
used on our platform. But maybe it could happen?
Don't want to cause any hidden regression.
The datasheet
On Thu, Sep 18, 2014 at 11:41:13AM +0200, Samuel Ortiz wrote:
Hi Mika,
On Thu, Sep 18, 2014 at 10:49:43AM +0300, Mika Westerberg wrote:
On Wed, Sep 17, 2014 at 03:47:01PM +0200, Loic Poulain wrote:
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io access mode.
Signed-off-by: Loic Poulain
---
v2: Apply over ff998356b644ebe723127bd9eec6040b59a4a4f6 + add Warning
drivers/pinctrl/pinctrl-baytrail.c | 5 -
1 file changed, 4 insertions(+), 1
Direct Irq En bit can be initialized to a bad value.
This bit has to be cleared for io access mode.
Signed-off-by: Loic Poulain loic.poul...@intel.com
---
v2: Apply over ff998356b644ebe723127bd9eec6040b59a4a4f6 + add Warning
drivers/pinctrl/pinctrl-baytrail.c | 5 -
1 file changed, 4
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