Re: [PATCHv2] x86: new Intel Atom SoC power management controller driver
ping... On 2014/6/17 10:18, Li, Aubrey wrote: > The Power Management Controller (PMC) controls many of the power > management features present in the SoC. This driver provides > interface to configure the Power Management Controller (PMC). > > This driver exposes PMC device state and sleep state residency > via debugfs: > /sys/kernel/debugfs/pmc_atom/dev_state > /sys/kernel/debugfs/pmc_atom/sleep_state > > This driver also provides a native power off function via PMC PCI > IO port. > > v2: > - Allow pmc_atom and lpc_ich to work at the same time. > > Signed-off-by: Aubrey Li > Signed-off-by: Lejun Zhu > Signed-off-by: Kasagar, Srinidhi > Reviewed-by: Rudramuni, Vishwesh M > Reviewed-by: Joe Perches > --- > arch/x86/Kconfig|4 + > arch/x86/include/asm/pmc_atom.h | 107 + > arch/x86/kernel/Makefile|1 + > arch/x86/kernel/pmc_atom.c | 323 > +++ > 4 files changed, 435 insertions(+) > create mode 100644 arch/x86/include/asm/pmc_atom.h > create mode 100644 arch/x86/kernel/pmc_atom.c > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index fcefdda..fa9c4b7 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -2404,6 +2404,10 @@ config IOSF_MBI > default m > depends on PCI > > +config PMC_ATOM > + def_bool y > +depends on PCI > + > source "net/Kconfig" > > source "drivers/Kconfig" > diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h > new file mode 100644 > index 000..c5c5d62 > --- /dev/null > +++ b/arch/x86/include/asm/pmc_atom.h > @@ -0,0 +1,107 @@ > +/* > + * Intel Atom SOC Power Management Controller Header File > + * Copyright (c) 2014, Intel Corporation. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + */ > + > +#ifndef PMC_ATOM_H > +#define PMC_ATOM_H > + > +/* ValleyView Power Control Unit PCI Device ID */ > +#define PCI_DEVICE_ID_VLV_PMC 0x0F1C > + > +/* PMC Memory mapped IO registers */ > +#define PMC_BASE_ADDR_OFFSET0x44 > +#define PMC_BASE_ADDR_MASK 0xFE00 > +#define PMC_MMIO_REG_LEN0x100 > +#define PMC_REG_BIT_WIDTH 32 > + > +/* BIOS uses FUNC_DIS to disable specific function */ > +#define PMC_FUNC_DIS0x34 > +#define PMC_FUNC_DIS_2 0x38 > + > +/* S0ix wake event control */ > +#define PMC_S0IX_WAKE_EN 0x3C > + > +#define BIT_LPC_CLOCK_RUNBIT(4) > +#define BIT_SHARED_IRQ_GPSC BIT(5) > +#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) > +#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) > +#define BIT_SHARED_IRQ_GPSS BIT(20) > + > +#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \ > + BIT_SHARED_IRQ_GPSC | \ > + BIT_ORED_DEDICATED_IRQ_GPSS | \ > + BIT_ORED_DEDICATED_IRQ_GPSC | \ > + BIT_SHARED_IRQ_GPSS) > + > +/* The timers acumulate time spent in sleep state */ > +#define PMC_S0IR_TMR0x80 > +#define PMC_S0I1_TMR0x84 > +#define PMC_S0I2_TMR0x88 > +#define PMC_S0I3_TMR0x8C > +#define PMC_S0_TMR 0x90 > +/* Sleep state counter is in units of of 32us */ > +#define PMC_TMR_SHIFT 5 > + > +/* These registers reflect D3 status of functions */ > +#define PMC_D3_STS_00xA0 > + > +#define BIT_LPSS1_F0_DMABIT(0) > +#define BIT_LPSS1_F1_PWM1 BIT(1) > +#define BIT_LPSS1_F2_PWM2 BIT(2) > +#define BIT_LPSS1_F3_HSUART1BIT(3) > +#define BIT_LPSS1_F4_HSUART2BIT(4) > +#define BIT_LPSS1_F5_SPIBIT(5) > +#define BIT_LPSS1_F6_XXXBIT(6) > +#define BIT_LPSS1_F7_XXXBIT(7) > +#define BIT_SCC_EMMCBIT(8) > +#define BIT_SCC_SDIOBIT(9) > +#define BIT_SCC_SDCARD BIT(10) > +#define BIT_SCC_MIPIBIT(11) > +#define BIT_HDA BIT(12) > +#define BIT_LPE BIT(13) > +#define BIT_OTG BIT(14) > +#define BIT_USH BIT(15) > +#define BIT_GBE BIT(16) > +#define BIT_SATABIT(17) > +#define BIT_USB_EHCIBIT(18) > +#define BIT_SEC BIT(19) > +#define BIT_PCIE_PORT0 BIT(20) > +#define BIT_PCIE_PORT1 BIT(21) > +#define
Re: [PATCHv2] x86: new Intel Atom SoC power management controller driver
ping... On 2014/6/17 10:18, Li, Aubrey wrote: The Power Management Controller (PMC) controls many of the power management features present in the SoC. This driver provides interface to configure the Power Management Controller (PMC). This driver exposes PMC device state and sleep state residency via debugfs: /sys/kernel/debugfs/pmc_atom/dev_state /sys/kernel/debugfs/pmc_atom/sleep_state This driver also provides a native power off function via PMC PCI IO port. v2: - Allow pmc_atom and lpc_ich to work at the same time. Signed-off-by: Aubrey Li aubrey...@linux.intel.com Signed-off-by: Lejun Zhu lejun@linux.intel.com Signed-off-by: Kasagar, Srinidhi srinidhi.kasa...@intel.com Reviewed-by: Rudramuni, Vishwesh M vishwesh.m.rudram...@intel.com Reviewed-by: Joe Perches j...@perches.com --- arch/x86/Kconfig|4 + arch/x86/include/asm/pmc_atom.h | 107 + arch/x86/kernel/Makefile|1 + arch/x86/kernel/pmc_atom.c | 323 +++ 4 files changed, 435 insertions(+) create mode 100644 arch/x86/include/asm/pmc_atom.h create mode 100644 arch/x86/kernel/pmc_atom.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fcefdda..fa9c4b7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2404,6 +2404,10 @@ config IOSF_MBI default m depends on PCI +config PMC_ATOM + def_bool y +depends on PCI + source net/Kconfig source drivers/Kconfig diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h new file mode 100644 index 000..c5c5d62 --- /dev/null +++ b/arch/x86/include/asm/pmc_atom.h @@ -0,0 +1,107 @@ +/* + * Intel Atom SOC Power Management Controller Header File + * Copyright (c) 2014, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef PMC_ATOM_H +#define PMC_ATOM_H + +/* ValleyView Power Control Unit PCI Device ID */ +#define PCI_DEVICE_ID_VLV_PMC 0x0F1C + +/* PMC Memory mapped IO registers */ +#define PMC_BASE_ADDR_OFFSET0x44 +#define PMC_BASE_ADDR_MASK 0xFE00 +#define PMC_MMIO_REG_LEN0x100 +#define PMC_REG_BIT_WIDTH 32 + +/* BIOS uses FUNC_DIS to disable specific function */ +#define PMC_FUNC_DIS0x34 +#define PMC_FUNC_DIS_2 0x38 + +/* S0ix wake event control */ +#define PMC_S0IX_WAKE_EN 0x3C + +#define BIT_LPC_CLOCK_RUNBIT(4) +#define BIT_SHARED_IRQ_GPSC BIT(5) +#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) +#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) +#define BIT_SHARED_IRQ_GPSS BIT(20) + +#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \ + BIT_SHARED_IRQ_GPSC | \ + BIT_ORED_DEDICATED_IRQ_GPSS | \ + BIT_ORED_DEDICATED_IRQ_GPSC | \ + BIT_SHARED_IRQ_GPSS) + +/* The timers acumulate time spent in sleep state */ +#define PMC_S0IR_TMR0x80 +#define PMC_S0I1_TMR0x84 +#define PMC_S0I2_TMR0x88 +#define PMC_S0I3_TMR0x8C +#define PMC_S0_TMR 0x90 +/* Sleep state counter is in units of of 32us */ +#define PMC_TMR_SHIFT 5 + +/* These registers reflect D3 status of functions */ +#define PMC_D3_STS_00xA0 + +#define BIT_LPSS1_F0_DMABIT(0) +#define BIT_LPSS1_F1_PWM1 BIT(1) +#define BIT_LPSS1_F2_PWM2 BIT(2) +#define BIT_LPSS1_F3_HSUART1BIT(3) +#define BIT_LPSS1_F4_HSUART2BIT(4) +#define BIT_LPSS1_F5_SPIBIT(5) +#define BIT_LPSS1_F6_XXXBIT(6) +#define BIT_LPSS1_F7_XXXBIT(7) +#define BIT_SCC_EMMCBIT(8) +#define BIT_SCC_SDIOBIT(9) +#define BIT_SCC_SDCARD BIT(10) +#define BIT_SCC_MIPIBIT(11) +#define BIT_HDA BIT(12) +#define BIT_LPE BIT(13) +#define BIT_OTG BIT(14) +#define BIT_USH BIT(15) +#define BIT_GBE BIT(16) +#define BIT_SATABIT(17) +#define BIT_USB_EHCIBIT(18) +#define BIT_SEC BIT(19) +#define BIT_PCIE_PORT0 BIT(20) +#define BIT_PCIE_PORT1 BIT(21) +#define BIT_PCIE_PORT2
[PATCHv2] x86: new Intel Atom SoC power management controller driver
The Power Management Controller (PMC) controls many of the power management features present in the SoC. This driver provides interface to configure the Power Management Controller (PMC). This driver exposes PMC device state and sleep state residency via debugfs: /sys/kernel/debugfs/pmc_atom/dev_state /sys/kernel/debugfs/pmc_atom/sleep_state This driver also provides a native power off function via PMC PCI IO port. v2: - Allow pmc_atom and lpc_ich to work at the same time. Signed-off-by: Aubrey Li Signed-off-by: Lejun Zhu Signed-off-by: Kasagar, Srinidhi Reviewed-by: Rudramuni, Vishwesh M Reviewed-by: Joe Perches --- arch/x86/Kconfig|4 + arch/x86/include/asm/pmc_atom.h | 107 + arch/x86/kernel/Makefile|1 + arch/x86/kernel/pmc_atom.c | 323 +++ 4 files changed, 435 insertions(+) create mode 100644 arch/x86/include/asm/pmc_atom.h create mode 100644 arch/x86/kernel/pmc_atom.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fcefdda..fa9c4b7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2404,6 +2404,10 @@ config IOSF_MBI default m depends on PCI +config PMC_ATOM + def_bool y +depends on PCI + source "net/Kconfig" source "drivers/Kconfig" diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h new file mode 100644 index 000..c5c5d62 --- /dev/null +++ b/arch/x86/include/asm/pmc_atom.h @@ -0,0 +1,107 @@ +/* + * Intel Atom SOC Power Management Controller Header File + * Copyright (c) 2014, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef PMC_ATOM_H +#define PMC_ATOM_H + +/* ValleyView Power Control Unit PCI Device ID */ +#definePCI_DEVICE_ID_VLV_PMC 0x0F1C + +/* PMC Memory mapped IO registers */ +#definePMC_BASE_ADDR_OFFSET0x44 +#definePMC_BASE_ADDR_MASK 0xFE00 +#definePMC_MMIO_REG_LEN0x100 +#definePMC_REG_BIT_WIDTH 32 + +/* BIOS uses FUNC_DIS to disable specific function */ +#definePMC_FUNC_DIS0x34 +#definePMC_FUNC_DIS_2 0x38 + +/* S0ix wake event control */ +#define PMC_S0IX_WAKE_EN 0x3C + +#define BIT_LPC_CLOCK_RUN BIT(4) +#defineBIT_SHARED_IRQ_GPSC BIT(5) +#defineBIT_ORED_DEDICATED_IRQ_GPSS BIT(18) +#defineBIT_ORED_DEDICATED_IRQ_GPSC BIT(19) +#defineBIT_SHARED_IRQ_GPSS BIT(20) + +#define PMC_WAKE_EN_SETTING~(BIT_LPC_CLOCK_RUN | \ + BIT_SHARED_IRQ_GPSC | \ + BIT_ORED_DEDICATED_IRQ_GPSS | \ + BIT_ORED_DEDICATED_IRQ_GPSC | \ + BIT_SHARED_IRQ_GPSS) + +/* The timers acumulate time spent in sleep state */ +#definePMC_S0IR_TMR0x80 +#definePMC_S0I1_TMR0x84 +#definePMC_S0I2_TMR0x88 +#definePMC_S0I3_TMR0x8C +#definePMC_S0_TMR 0x90 +/* Sleep state counter is in units of of 32us */ +#definePMC_TMR_SHIFT 5 + +/* These registers reflect D3 status of functions */ +#definePMC_D3_STS_00xA0 + +#defineBIT_LPSS1_F0_DMABIT(0) +#defineBIT_LPSS1_F1_PWM1 BIT(1) +#defineBIT_LPSS1_F2_PWM2 BIT(2) +#defineBIT_LPSS1_F3_HSUART1BIT(3) +#defineBIT_LPSS1_F4_HSUART2BIT(4) +#defineBIT_LPSS1_F5_SPIBIT(5) +#defineBIT_LPSS1_F6_XXXBIT(6) +#defineBIT_LPSS1_F7_XXXBIT(7) +#defineBIT_SCC_EMMCBIT(8) +#defineBIT_SCC_SDIOBIT(9) +#defineBIT_SCC_SDCARD BIT(10) +#defineBIT_SCC_MIPIBIT(11) +#defineBIT_HDA BIT(12) +#defineBIT_LPE BIT(13) +#defineBIT_OTG BIT(14) +#defineBIT_USH BIT(15) +#defineBIT_GBE BIT(16) +#defineBIT_SATABIT(17) +#defineBIT_USB_EHCIBIT(18) +#defineBIT_SEC BIT(19) +#defineBIT_PCIE_PORT0 BIT(20) +#defineBIT_PCIE_PORT1 BIT(21) +#defineBIT_PCIE_PORT2 BIT(22) +#defineBIT_PCIE_PORT3 BIT(23) +#defineBIT_LPSS2_F0_DMABIT(24) +#defineBIT_LPSS2_F1_I2C1 BIT(25) +#defineBIT_LPSS2_F2_I2C2
[PATCHv2] x86: new Intel Atom SoC power management controller driver
The Power Management Controller (PMC) controls many of the power management features present in the SoC. This driver provides interface to configure the Power Management Controller (PMC). This driver exposes PMC device state and sleep state residency via debugfs: /sys/kernel/debugfs/pmc_atom/dev_state /sys/kernel/debugfs/pmc_atom/sleep_state This driver also provides a native power off function via PMC PCI IO port. v2: - Allow pmc_atom and lpc_ich to work at the same time. Signed-off-by: Aubrey Li aubrey...@linux.intel.com Signed-off-by: Lejun Zhu lejun@linux.intel.com Signed-off-by: Kasagar, Srinidhi srinidhi.kasa...@intel.com Reviewed-by: Rudramuni, Vishwesh M vishwesh.m.rudram...@intel.com Reviewed-by: Joe Perches j...@perches.com --- arch/x86/Kconfig|4 + arch/x86/include/asm/pmc_atom.h | 107 + arch/x86/kernel/Makefile|1 + arch/x86/kernel/pmc_atom.c | 323 +++ 4 files changed, 435 insertions(+) create mode 100644 arch/x86/include/asm/pmc_atom.h create mode 100644 arch/x86/kernel/pmc_atom.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fcefdda..fa9c4b7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2404,6 +2404,10 @@ config IOSF_MBI default m depends on PCI +config PMC_ATOM + def_bool y +depends on PCI + source net/Kconfig source drivers/Kconfig diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h new file mode 100644 index 000..c5c5d62 --- /dev/null +++ b/arch/x86/include/asm/pmc_atom.h @@ -0,0 +1,107 @@ +/* + * Intel Atom SOC Power Management Controller Header File + * Copyright (c) 2014, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef PMC_ATOM_H +#define PMC_ATOM_H + +/* ValleyView Power Control Unit PCI Device ID */ +#definePCI_DEVICE_ID_VLV_PMC 0x0F1C + +/* PMC Memory mapped IO registers */ +#definePMC_BASE_ADDR_OFFSET0x44 +#definePMC_BASE_ADDR_MASK 0xFE00 +#definePMC_MMIO_REG_LEN0x100 +#definePMC_REG_BIT_WIDTH 32 + +/* BIOS uses FUNC_DIS to disable specific function */ +#definePMC_FUNC_DIS0x34 +#definePMC_FUNC_DIS_2 0x38 + +/* S0ix wake event control */ +#define PMC_S0IX_WAKE_EN 0x3C + +#define BIT_LPC_CLOCK_RUN BIT(4) +#defineBIT_SHARED_IRQ_GPSC BIT(5) +#defineBIT_ORED_DEDICATED_IRQ_GPSS BIT(18) +#defineBIT_ORED_DEDICATED_IRQ_GPSC BIT(19) +#defineBIT_SHARED_IRQ_GPSS BIT(20) + +#define PMC_WAKE_EN_SETTING~(BIT_LPC_CLOCK_RUN | \ + BIT_SHARED_IRQ_GPSC | \ + BIT_ORED_DEDICATED_IRQ_GPSS | \ + BIT_ORED_DEDICATED_IRQ_GPSC | \ + BIT_SHARED_IRQ_GPSS) + +/* The timers acumulate time spent in sleep state */ +#definePMC_S0IR_TMR0x80 +#definePMC_S0I1_TMR0x84 +#definePMC_S0I2_TMR0x88 +#definePMC_S0I3_TMR0x8C +#definePMC_S0_TMR 0x90 +/* Sleep state counter is in units of of 32us */ +#definePMC_TMR_SHIFT 5 + +/* These registers reflect D3 status of functions */ +#definePMC_D3_STS_00xA0 + +#defineBIT_LPSS1_F0_DMABIT(0) +#defineBIT_LPSS1_F1_PWM1 BIT(1) +#defineBIT_LPSS1_F2_PWM2 BIT(2) +#defineBIT_LPSS1_F3_HSUART1BIT(3) +#defineBIT_LPSS1_F4_HSUART2BIT(4) +#defineBIT_LPSS1_F5_SPIBIT(5) +#defineBIT_LPSS1_F6_XXXBIT(6) +#defineBIT_LPSS1_F7_XXXBIT(7) +#defineBIT_SCC_EMMCBIT(8) +#defineBIT_SCC_SDIOBIT(9) +#defineBIT_SCC_SDCARD BIT(10) +#defineBIT_SCC_MIPIBIT(11) +#defineBIT_HDA BIT(12) +#defineBIT_LPE BIT(13) +#defineBIT_OTG BIT(14) +#defineBIT_USH BIT(15) +#defineBIT_GBE BIT(16) +#defineBIT_SATABIT(17) +#defineBIT_USB_EHCIBIT(18) +#defineBIT_SEC BIT(19) +#defineBIT_PCIE_PORT0 BIT(20) +#defineBIT_PCIE_PORT1 BIT(21) +#defineBIT_PCIE_PORT2 BIT(22) +#defineBIT_PCIE_PORT3 BIT(23) +#define
