On 06/01/17 02:59, Mark Rutland wrote:
> On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote:
>> +internal-regs {
>> +coreclk: mvebu-sar@18230 {
>> +compatible = "marvell,mv98dx3236-core-clock";
>> +};
>> +
>>
On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote:
> + internal-regs {
> + coreclk: mvebu-sar@18230 {
> + compatible = "marvell,mv98dx3236-core-clock";
> + };
> +
> + cpuclk: clock-comple
On 05/01/17 17:06, Florian Fainelli wrote:
> Le 01/04/17 à 19:36, Chris Packham a écrit :
>> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
>> with integrated CPUs. They are similar to the Armada XP SoCs but have
>> different I/O interfaces.
>>
>> Signed-off-by: Chris Packha
Le 01/04/17 à 19:36, Chris Packham a écrit :
> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
> with integrated CPUs. They are similar to the Armada XP SoCs but have
> different I/O interfaces.
>
> Signed-off-by: Chris Packham
> ---
> +
> + switch {
> +
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham
---
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
984251 ar
5 matches
Mail list logo
