Re: [Question] How to implement GPIO driver for sparse hw numbers?
Hi Linus, 2015-07-15 7:04 GMT+09:00 Linus Walleij : > On Fri, Jun 19, 2015 at 5:27 AM, Masahiro Yamada > wrote: > >> In my understanding, the GPIO driver framework requires that >> the hw numbers should be contiguous within each GPIO chip. > > Yes but noone says that .request() to the driver has to succeed > on every GPIO so just cover all GPIOs from 0 to 307 with > your GPIO chip and then implement your "holes" in the GPIO > range from 0 to 307 by letting .request() fail. Thanks, At first I also thought about it, but finally I did not adopt it. Having holes in the GPIO range is not handy because: [1] When we map a gpio range into a pin range, we must divide "gpio-ranges" property into many lines gpio-ranges = http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Question] How to implement GPIO driver for sparse hw numbers?
Hi Linus, 2015-07-15 7:04 GMT+09:00 Linus Walleij linus.wall...@linaro.org: On Fri, Jun 19, 2015 at 5:27 AM, Masahiro Yamada yamada.masah...@socionext.com wrote: In my understanding, the GPIO driver framework requires that the hw numbers should be contiguous within each GPIO chip. Yes but noone says that .request() to the driver has to succeed on every GPIO so just cover all GPIOs from 0 to 307 with your GPIO chip and then implement your holes in the GPIO range from 0 to 307 by letting .request() fail. Thanks, At first I also thought about it, but finally I did not adopt it. Having holes in the GPIO range is not handy because: [1] When we map a gpio range into a pin range, we must divide gpio-ranges property into many lines gpio-ranges = phandle 0x 8 phandle 10 (x+8) 8 phandle 20 (x+16) 8 phandle 30 (x+24) 8 ... [2] implementation of .set_multiple() gets more complicated -- Best Regards Masahiro Yamada -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Question] How to implement GPIO driver for sparse hw numbers?
On Fri, Jun 19, 2015 at 5:27 AM, Masahiro Yamada wrote: > In my understanding, the GPIO driver framework requires that > the hw numbers should be contiguous within each GPIO chip. Yes but noone says that .request() to the driver has to succeed on every GPIO so just cover all GPIOs from 0 to 307 with your GPIO chip and then implement your "holes" in the GPIO range from 0 to 307 by letting .request() fail. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Question] How to implement GPIO driver for sparse hw numbers?
On Fri, Jun 19, 2015 at 5:27 AM, Masahiro Yamada yamada.masah...@socionext.com wrote: In my understanding, the GPIO driver framework requires that the hw numbers should be contiguous within each GPIO chip. Yes but noone says that .request() to the driver has to succeed on every GPIO so just cover all GPIOs from 0 to 307 with your GPIO chip and then implement your holes in the GPIO range from 0 to 307 by letting .request() fail. Yours, Linus Walleij -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[Question] How to implement GPIO driver for sparse hw numbers?
Hi GPIO experts,
I am trying to implement a new GPIO driver for a new SoC.
I'd like to consult experts how to solve my problem.
According to the hardware specification book,
the GPIO ports on my SoC are labelled from PORT0 to PORT307 as follows:
PORT0, PORT1, PORT2, PORT7,--> register offset 0x0
PORT10, PORT11, PORT12, ..., PORT17--> register offset 0x8
PORT20, PORT21, PORT22, ..., PORT27, --> register offset 0x10
...
PORT290, PORT291, PORT292, ... PORT297 --> register offset 0xe8
PORT300, PORT301, PORT302, ... PORT307 --> register offset 0x90
Unfortunately, the port numbers are not contiguous.
The port numbers with 8 or 9 in the one's place
(such as PORT8, PORT9, PORT18, PORT19, ...) are missing.
In my understanding, the GPIO driver framework requires that
the hw numbers should be contiguous within each GPIO chip.
If I try to follow this rule, the hwnum given to GPIOLIB functions
does not correspond to the port documented in the hardware specification.
gpiochip_get_desc(chip, 0); /* get descripter of PORT0 */
gpiochip_get_desc(chip, 1); /* get descripter of PORT1 */
...
gpiochip_get_desc(chip, 7); /* get descripter of PORT7 */
gpiochip_get_desc(chip, 8); /* get descripter of PORT10 */ /* confusing! */
gpiochip_get_desc(chip, 9); /* get descripter of PORT11 */ /* confusing! */
gpiochip_get_desc(chip, 10); /* get descripter of PORT12 */ /*
confusing! */
...
One solution I have come up with is to divide the GPIO chip into 31 banks,
with 8 ports in each.
But, I hesitate to describe 31 nodes in my device tree.
port0x : gpio@5500 {
compatible = ...
reg = <0x5500 0x8>;
};
port1x : gpio@5508 {
compatible = ...
reg = <0x5508 0x8>;
};
...
port29x : gpio@558c {
compatible = ...
reg = <0x558c 0x8>;
};
port30x : gpio@5590 {
compatible = ...
reg = <0x5590 0x8>;
};
Any good ideas?
Thanks,
--
Best Regards
Masahiro Yamada
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[Question] How to implement GPIO driver for sparse hw numbers?
Hi GPIO experts,
I am trying to implement a new GPIO driver for a new SoC.
I'd like to consult experts how to solve my problem.
According to the hardware specification book,
the GPIO ports on my SoC are labelled from PORT0 to PORT307 as follows:
PORT0, PORT1, PORT2, PORT7,-- register offset 0x0
PORT10, PORT11, PORT12, ..., PORT17-- register offset 0x8
PORT20, PORT21, PORT22, ..., PORT27, -- register offset 0x10
...
PORT290, PORT291, PORT292, ... PORT297 -- register offset 0xe8
PORT300, PORT301, PORT302, ... PORT307 -- register offset 0x90
Unfortunately, the port numbers are not contiguous.
The port numbers with 8 or 9 in the one's place
(such as PORT8, PORT9, PORT18, PORT19, ...) are missing.
In my understanding, the GPIO driver framework requires that
the hw numbers should be contiguous within each GPIO chip.
If I try to follow this rule, the hwnum given to GPIOLIB functions
does not correspond to the port documented in the hardware specification.
gpiochip_get_desc(chip, 0); /* get descripter of PORT0 */
gpiochip_get_desc(chip, 1); /* get descripter of PORT1 */
...
gpiochip_get_desc(chip, 7); /* get descripter of PORT7 */
gpiochip_get_desc(chip, 8); /* get descripter of PORT10 */ /* confusing! */
gpiochip_get_desc(chip, 9); /* get descripter of PORT11 */ /* confusing! */
gpiochip_get_desc(chip, 10); /* get descripter of PORT12 */ /*
confusing! */
...
One solution I have come up with is to divide the GPIO chip into 31 banks,
with 8 ports in each.
But, I hesitate to describe 31 nodes in my device tree.
port0x : gpio@5500 {
compatible = ...
reg = 0x5500 0x8;
};
port1x : gpio@5508 {
compatible = ...
reg = 0x5508 0x8;
};
...
port29x : gpio@558c {
compatible = ...
reg = 0x558c 0x8;
};
port30x : gpio@5590 {
compatible = ...
reg = 0x5590 0x8;
};
Any good ideas?
Thanks,
--
Best Regards
Masahiro Yamada
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
