On 2017/1/3 20:00, Lorenzo Pieralisi wrote:
> On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
>>
>> This patch will
On 2017/1/3 20:00, Lorenzo Pieralisi wrote:
> On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
>>
>> This patch will
On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
> each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
> bus
On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
> each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
> bus
On 2017/1/3 14:39, Tomasz Nowicki wrote:
> On 22.12.2016 10:07, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
>>
>> This patch will support this kind of
On 2017/1/3 14:39, Tomasz Nowicki wrote:
> On 22.12.2016 10:07, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
>>
>> This patch will support this kind of
On 22.12.2016 10:07, Zhou Wang wrote:
Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each
host bridge should be in the coverage of bus range of related PCIe segment.
This patch will support this kind of scenario:
MCFG:
bus range: 0x00~0xff.
segment:
On 22.12.2016 10:07, Zhou Wang wrote:
Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each
host bridge should be in the coverage of bus range of related PCIe segment.
This patch will support this kind of scenario:
MCFG:
bus range: 0x00~0xff.
segment:
On 2016/12/22 17:07, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
> each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
> bus range: 0x00~0xff.
>
On 2016/12/22 17:07, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
> each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
> bus range: 0x00~0xff.
>
Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each
host bridge should be in the coverage of bus range of related PCIe segment.
This patch will support this kind of scenario:
MCFG:
bus range: 0x00~0xff.
segment: 0.
DSDT:
host bridge 1:
Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each
host bridge should be in the coverage of bus range of related PCIe segment.
This patch will support this kind of scenario:
MCFG:
bus range: 0x00~0xff.
segment: 0.
DSDT:
host bridge 1:
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