On 16.11.2017 12:45, Mark Brown wrote:
On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote:
+#ifdef CONFIG_SOC_SAM_V4_V5
+ /*
+* On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT
+* model, hence the cache aliases issue can occur when buffers are
+
On 16.11.2017 12:45, Mark Brown wrote:
On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote:
+#ifdef CONFIG_SOC_SAM_V4_V5
+ /*
+* On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT
+* model, hence the cache aliases issue can occur when buffers are
+
On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote:
> +#ifdef CONFIG_SOC_SAM_V4_V5
> + /*
> + * On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT
> + * model, hence the cache aliases issue can occur when buffers are
> + * allocated from DMA-unsafe
On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote:
> +#ifdef CONFIG_SOC_SAM_V4_V5
> + /*
> + * On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT
> + * model, hence the cache aliases issue can occur when buffers are
> + * allocated from DMA-unsafe
On 15.11.2017 21:01, Trent Piepho wrote:
On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote:
If the cache model is VIVT, DMA data transfers may not be valid and to
ensure the validity of the data cache must be flushed and invalidated.
Signed-off-by: Radu Pirea
On 15.11.2017 21:01, Trent Piepho wrote:
On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote:
If the cache model is VIVT, DMA data transfers may not be valid and to
ensure the validity of the data cache must be flushed and invalidated.
Signed-off-by: Radu Pirea
+#ifdef CONFIG_SOC_SAM_V4_V5
On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote:
> If the cache model is VIVT, DMA data transfers may not be valid and to
> ensure the validity of the data cache must be flushed and invalidated.
>
> Signed-off-by: Radu Pirea
>
> +#ifdef CONFIG_SOC_SAM_V4_V5
> +
On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote:
> If the cache model is VIVT, DMA data transfers may not be valid and to
> ensure the validity of the data cache must be flushed and invalidated.
>
> Signed-off-by: Radu Pirea
>
> +#ifdef CONFIG_SOC_SAM_V4_V5
> + /*
> + * On Atmel
If the cache model is VIVT, DMA data transfers may not be valid and to
ensure the validity of the data cache must be flushed and invalidated.
Signed-off-by: Radu Pirea
---
drivers/spi/spi-atmel.c | 20
1 file changed, 20 insertions(+)
diff --git
If the cache model is VIVT, DMA data transfers may not be valid and to
ensure the validity of the data cache must be flushed and invalidated.
Signed-off-by: Radu Pirea
---
drivers/spi/spi-atmel.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/spi/spi-atmel.c
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