Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-12-08 Thread Radu Nicolae Pirea
On 16.11.2017 12:45, Mark Brown wrote: On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote: +#ifdef CONFIG_SOC_SAM_V4_V5 + /* +* On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT +* model, hence the cache aliases issue can occur when buffers are +

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-12-08 Thread Radu Nicolae Pirea
On 16.11.2017 12:45, Mark Brown wrote: On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote: +#ifdef CONFIG_SOC_SAM_V4_V5 + /* +* On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT +* model, hence the cache aliases issue can occur when buffers are +

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-16 Thread Mark Brown
On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote: > +#ifdef CONFIG_SOC_SAM_V4_V5 > + /* > + * On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT > + * model, hence the cache aliases issue can occur when buffers are > + * allocated from DMA-unsafe

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-16 Thread Mark Brown
On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote: > +#ifdef CONFIG_SOC_SAM_V4_V5 > + /* > + * On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT > + * model, hence the cache aliases issue can occur when buffers are > + * allocated from DMA-unsafe

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-16 Thread Radu Nicolae Pirea
On 15.11.2017 21:01, Trent Piepho wrote: On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote: If the cache model is VIVT, DMA data transfers may not be valid and to ensure the validity of the data cache must be flushed and invalidated. Signed-off-by: Radu Pirea

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-16 Thread Radu Nicolae Pirea
On 15.11.2017 21:01, Trent Piepho wrote: On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote: If the cache model is VIVT, DMA data transfers may not be valid and to ensure the validity of the data cache must be flushed and invalidated. Signed-off-by: Radu Pirea +#ifdef CONFIG_SOC_SAM_V4_V5

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-15 Thread Trent Piepho
On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote: > If the cache model is VIVT, DMA data transfers may not be valid and to > ensure the validity of the data cache must be flushed and invalidated. > > Signed-off-by: Radu Pirea > > +#ifdef CONFIG_SOC_SAM_V4_V5 > +

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-15 Thread Trent Piepho
On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote: > If the cache model is VIVT, DMA data transfers may not be valid and to > ensure the validity of the data cache must be flushed and invalidated. > > Signed-off-by: Radu Pirea > > +#ifdef CONFIG_SOC_SAM_V4_V5 > + /* > + * On Atmel

[RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-15 Thread Radu Pirea
If the cache model is VIVT, DMA data transfers may not be valid and to ensure the validity of the data cache must be flushed and invalidated. Signed-off-by: Radu Pirea --- drivers/spi/spi-atmel.c | 20 1 file changed, 20 insertions(+) diff --git

[RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-15 Thread Radu Pirea
If the cache model is VIVT, DMA data transfers may not be valid and to ensure the validity of the data cache must be flushed and invalidated. Signed-off-by: Radu Pirea --- drivers/spi/spi-atmel.c | 20 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-atmel.c