Re: [RFC PATCH 4/6] spi: cadence-qspi: Use PHY for DAC reads if possible

2021-03-12 Thread Pratyush Yadav
On 12/03/21 09:13AM, tudor.amba...@microchip.com wrote: > On 3/11/21 9:12 PM, Pratyush Yadav wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > Check if a read is eligible for PHY and if it is, enable PHY and DQS. > > DQS as in data

Re: [RFC PATCH 4/6] spi: cadence-qspi: Use PHY for DAC reads if possible

2021-03-12 Thread Tudor.Ambarus
On 3/11/21 9:12 PM, Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Check if a read is eligible for PHY and if it is, enable PHY and DQS. DQS as in data strobe? Shouldn't the upper layer inform the QSPI controller whether

[RFC PATCH 4/6] spi: cadence-qspi: Use PHY for DAC reads if possible

2021-03-11 Thread Pratyush Yadav
Check if a read is eligible for PHY and if it is, enable PHY and DQS. Since PHY reads only work at an address that is 16-byte aligned and of size that is a multiple of 16 bytes, read the starting and ending unaligned portions without PHY, and only enable PHY for the middle part. Signed-off-by: