Re: [RFC PATCH v4 10/13] soc: ti: Add MSI domain support for K3 Interrupt Aggregator

2019-01-15 Thread Nishanth Menon
On 11:43-20181227, Lokesh Vutla wrote:
> With the system coprocessor managing the range allocation of the
> inputs to Interrupt Aggregator, it is difficult to represent
> the device IRQs from DT.
> 
> The suggestion is to use MSI in such cases where devices wants
> to allocate and group interrupts dynamically.
> 
> Create a MSI domain bus layer that allocates and frees MSIs for
> a device.
> 
> APIs that are implemented are:
> - inta_msi_create_irq_domain() that creates a MSI domain
> - inta_msi_domain_alloc_group_irqs() that creates MSIs for the
>   specified device and source indexes. All these are expected to
>   be grouped by the parent interrupt controller to MSI domain.
> - inta_msi_domain_free_group_irqs() frees the grouped irqs.
> 
> Signed-off-by: Lokesh Vutla 
> ---
> 
> - May be the same functionaly can be included in platform msi. But I would
>   like to get a feedback on the approach.
> 
>  drivers/soc/ti/Kconfig |   6 +
>  drivers/soc/ti/Makefile|   1 +
>  drivers/soc/ti/k3_inta_msi.c   | 193 +
>  include/linux/irqdomain.h  |   1 +
>  include/linux/msi.h|   6 +
>  include/linux/soc/ti/k3_inta_msi.h |  22 
>  6 files changed, 229 insertions(+)
>  create mode 100644 drivers/soc/ti/k3_inta_msi.c
>  create mode 100644 include/linux/soc/ti/k3_inta_msi.h

Did we miss maintainer file?

-- 
Regards,
Nishanth Menon


[RFC PATCH v4 10/13] soc: ti: Add MSI domain support for K3 Interrupt Aggregator

2018-12-26 Thread Lokesh Vutla
With the system coprocessor managing the range allocation of the
inputs to Interrupt Aggregator, it is difficult to represent
the device IRQs from DT.

The suggestion is to use MSI in such cases where devices wants
to allocate and group interrupts dynamically.

Create a MSI domain bus layer that allocates and frees MSIs for
a device.

APIs that are implemented are:
- inta_msi_create_irq_domain() that creates a MSI domain
- inta_msi_domain_alloc_group_irqs() that creates MSIs for the
  specified device and source indexes. All these are expected to
  be grouped by the parent interrupt controller to MSI domain.
- inta_msi_domain_free_group_irqs() frees the grouped irqs.

Signed-off-by: Lokesh Vutla 
---

- May be the same functionaly can be included in platform msi. But I would
  like to get a feedback on the approach.

 drivers/soc/ti/Kconfig |   6 +
 drivers/soc/ti/Makefile|   1 +
 drivers/soc/ti/k3_inta_msi.c   | 193 +
 include/linux/irqdomain.h  |   1 +
 include/linux/msi.h|   6 +
 include/linux/soc/ti/k3_inta_msi.h |  22 
 6 files changed, 229 insertions(+)
 create mode 100644 drivers/soc/ti/k3_inta_msi.c
 create mode 100644 include/linux/soc/ti/k3_inta_msi.h

diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
index be4570baad96..7640490c2a6a 100644
--- a/drivers/soc/ti/Kconfig
+++ b/drivers/soc/ti/Kconfig
@@ -73,4 +73,10 @@ config TI_SCI_PM_DOMAINS
  called ti_sci_pm_domains. Note this is needed early in boot before
  rootfs may be available.
 
+config K3_INTA_MSI_DOMAIN
+   bool
+   select GENERIC_MSI_IRQ_DOMAIN
+   help
+ Driver to enable Interrupt Aggregator specific MSI Domain.
+
 endif # SOC_TI
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index a22edc0b258a..152b195273ee 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA)+= knav_dma.o
 obj-$(CONFIG_AMX3_PM)  += pm33xx.o
 obj-$(CONFIG_WKUP_M3_IPC)  += wkup_m3_ipc.o
 obj-$(CONFIG_TI_SCI_PM_DOMAINS)+= ti_sci_pm_domains.o
+obj-$(CONFIG_K3_INTA_MSI_DOMAIN)   += k3_inta_msi.o
diff --git a/drivers/soc/ti/k3_inta_msi.c b/drivers/soc/ti/k3_inta_msi.c
new file mode 100644
index ..4658a9f9e1c4
--- /dev/null
+++ b/drivers/soc/ti/k3_inta_msi.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Texas Instruments' K3 Interrupt Aggregator driver MSI support
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef GENERIC_MSI_DOMAIN_OPS
+
+#define TI_SCI_DEV_ID_MASK 0x
+#define TI_SCI_DEV_ID_SHIFT16
+#define TI_SCI_IRQ_ID_MASK 0x
+#define TI_SCI_IRQ_ID_SHIFT0
+
+#define TO_HWIRQ(id, index)(((id & TI_SCI_DEV_ID_MASK) << \
+TI_SCI_DEV_ID_SHIFT) | \
+   (index & TI_SCI_IRQ_ID_MASK))
+static void inta_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
+{
+   arg->desc = desc;
+   arg->hwirq = TO_HWIRQ(desc->inta.dev_id, desc->inta.msi_index);
+}
+#else
+#define inta_msi_set_desc NULL
+#endif
+
+static void inta_msi_update_dom_ops(struct msi_domain_info *info)
+{
+   struct msi_domain_ops *ops = info->ops;
+
+   BUG_ON(!ops);
+
+   if (ops->set_desc == NULL)
+   ops->set_desc = inta_msi_set_desc;
+}
+
+static void inta_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
+{
+}
+
+static void inta_msi_compose_msi_msg(struct irq_data *data,
+struct msi_msg *msg)
+{
+}
+
+static void inta_msi_update_chip_ops(struct msi_domain_info *info)
+{
+   struct irq_chip *chip = info->chip;
+
+   BUG_ON(!chip);
+   if (!chip->irq_mask)
+   chip->irq_mask = irq_chip_mask_parent;
+   if (!chip->irq_unmask)
+   chip->irq_unmask = irq_chip_unmask_parent;
+   if (!chip->irq_eoi)
+   chip->irq_eoi = irq_chip_eoi_parent;
+   if (!chip->irq_set_affinity)
+   chip->irq_set_affinity = msi_domain_set_affinity;
+   if (!chip->irq_write_msi_msg)
+   chip->irq_write_msi_msg = inta_msi_write_msg;
+   if (!chip->irq_compose_msi_msg)
+   chip->irq_compose_msi_msg = inta_msi_compose_msi_msg;
+}
+
+struct irq_domain *inta_msi_create_irq_domain(struct fwnode_handle *fwnode,
+ struct msi_domain_info *info,
+ struct irq_domain *parent)
+{
+   struct irq_domain *domain;
+
+   if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
+   inta_msi_update_dom_ops(info);
+   if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
+   inta_msi_update_chip_ops(info);
+
+   domain = msi_create_irq_domain(fwnode, info, pare