On 05/03/2021 18:04, Hector Martin wrote:
> On 06/03/2021 00.28, Andy Shevchenko wrote:
>>> + case TYPE_APPLE_S5L:
>>> + WARN_ON(1); // No DMA
>>
>> Oh, no, please use the ONCE variant.
>
> Thanks, changing this for v4.
>
>>
>> ...
>>
>>> + /* Apple types use these bits
On 06/03/2021 00.28, Andy Shevchenko wrote:
+ case TYPE_APPLE_S5L:
+ WARN_ON(1); // No DMA
Oh, no, please use the ONCE variant.
Thanks, changing this for v4.
...
+ /* Apple types use these bits for IRQ masks */
+ if (ourport->info->type != TYPE_APPLE_S5L)
On Thu, Mar 4, 2021 at 11:42 PM Hector Martin wrote:
>
> Apple SoCs are a distant descendant of Samsung designs and use yet
> another variant of their UART style, with different interrupt handling.
>
> In particular, this variant has the following differences with existing
> ones:
>
> * It
On 04/03/2021 22:38, Hector Martin wrote:
> Apple SoCs are a distant descendant of Samsung designs and use yet
> another variant of their UART style, with different interrupt handling.
>
> In particular, this variant has the following differences with existing
> ones:
>
> * It includes a
Apple SoCs are a distant descendant of Samsung designs and use yet
another variant of their UART style, with different interrupt handling.
In particular, this variant has the following differences with existing
ones:
* It includes a built-in interrupt controller with different registers,
using
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