On Tue, Apr 04, 2017 at 10:55:00AM +0300, Daniel Baluta wrote:
>
>
> On Mon, Apr 3, 2017 at 4:54 PM, Charles Keepax
> wrote:
> > On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
> >> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
> >>
On Tue, Apr 04, 2017 at 10:55:00AM +0300, Daniel Baluta wrote:
>
>
> On Mon, Apr 3, 2017 at 4:54 PM, Charles Keepax
> wrote:
> > On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
> >> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
> >> wrote:
> > Is the problem here that the PLL
On Mon, Apr 3, 2017 at 4:54 PM, Charles Keepax
wrote:
> On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
>> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
>> wrote:
>> > On Mon, Apr 03, 2017 at 04:16:23PM
On Mon, Apr 3, 2017 at 4:54 PM, Charles Keepax
wrote:
> On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
>> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
>> wrote:
>> > On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
>> > Does this problem still remain after the
On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
> wrote:
> > On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
> > Does this problem still remain after the relaxed clock
> >
On Mon, Apr 03, 2017 at 04:39:40PM +0300, Daniel Baluta wrote:
> On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
> wrote:
> > On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
> > Does this problem still remain after the relaxed clock
> > computation? The maths you quote depends on
On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
wrote:
> On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
>> On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote:
>> > On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
On Mon, Apr 3, 2017 at 4:34 PM, Charles Keepax
wrote:
> On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
>> On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote:
>> > On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
>> >> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang
On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
> On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote:
> > On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
> >> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
> > I found it can't generate
On Mon, Apr 03, 2017 at 04:16:23PM +0300, Daniel Baluta wrote:
> On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote:
> > On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
> >> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
> > I found it can't generate bclk for S20_3LE data
On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote:
> On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
>> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
>>
>> > + for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) {
>> > + if (wm8960->sysclk ==
On Thu, Jan 15, 2015 at 3:34 PM, Zidan Wang wrote:
> On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
>> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
>>
>> > + for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) {
>> > + if (wm8960->sysclk == lrclk * dac_divs[i]) {
>>
On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
> On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
>
> > + for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) {
> > + if (wm8960->sysclk == lrclk * dac_divs[i]) {
> > + for (j = 0; j <
On Wed, Jan 14, 2015 at 07:27:03PM +, Mark Brown wrote:
On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
+ for (i = 0; i ARRAY_SIZE(dac_divs); ++i) {
+ if (wm8960-sysclk == lrclk * dac_divs[i]) {
+ for (j = 0; j ARRAY_SIZE(bclk_divs); ++j) {
On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
> + for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) {
> + if (wm8960->sysclk == lrclk * dac_divs[i]) {
> + for (j = 0; j < ARRAY_SIZE(bclk_divs); ++j) {
> + if (wm8960->sysclk ==
On Wed, Jan 07, 2015 at 03:31:45PM +0800, Zidan Wang wrote:
+ for (i = 0; i ARRAY_SIZE(dac_divs); ++i) {
+ if (wm8960-sysclk == lrclk * dac_divs[i]) {
+ for (j = 0; j ARRAY_SIZE(bclk_divs); ++j) {
+ if (wm8960-sysclk ==
From: Zidan Wang
wm8960 codec driver missing configure its bit clock and frame clock, so add
support for it. It will calculate a appropriate frequency dividing ratio
according to the system clock, bit clock and frame clock, then set the
corresponding registers.
Signed-off-by: Zidan Wang
---
From: Zidan Wang b50...@freescale.com
wm8960 codec driver missing configure its bit clock and frame clock, so add
support for it. It will calculate a appropriate frequency dividing ratio
according to the system clock, bit clock and frame clock, then set the
corresponding registers.
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