于 2018年7月25日 GMT+08:00 下午11:31:26, Rob Herring 写到:
>On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
>> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng
>wrote:
>> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > external USB3 pins of the SoC.
>> >
>> > Add
于 2018年7月25日 GMT+08:00 下午11:31:26, Rob Herring 写到:
>On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
>> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng
>wrote:
>> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > external USB3 pins of the SoC.
>> >
>> > Add
On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng wrote:
> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> > external USB3 pins of the SoC.
> >
> > Add a device tree binding for the PHY.
> >
> > Signed-off-by:
On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng wrote:
> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> > external USB3 pins of the SoC.
> >
> > Add a device tree binding for the PHY.
> >
> > Signed-off-by:
4 matches
Mail list logo