* Siddha, Suresh B <[EMAIL PROTECTED]> wrote:
> In the presence of SMT, newly idle balance was never happening for
> multi-core and SMP domains(even when both the logical siblings are
> idle).
>
> If thread 0 is already idle and when thread 1 is about to go to idle,
> newly idle load balance
* Siddha, Suresh B [EMAIL PROTECTED] wrote:
In the presence of SMT, newly idle balance was never happening for
multi-core and SMP domains(even when both the logical siblings are
idle).
If thread 0 is already idle and when thread 1 is about to go to idle,
newly idle load balance always
In the presence of SMT, newly idle balance was never happening for multi-core
and SMP domains(even when both the logical siblings are idle).
If thread 0 is already idle and when thread 1 is about to go to idle, newly
idle load balance always think that one of the threads is not idle and skips
In the presence of SMT, newly idle balance was never happening for multi-core
and SMP domains(even when both the logical siblings are idle).
If thread 0 is already idle and when thread 1 is about to go to idle, newly
idle load balance always think that one of the threads is not idle and skips
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