Bjorn,
You have the following registers to consider (for P4/Core):
#define MSR_IA32_PEBS_ENABLE0x03f1
#define MSR_CORE_PERF_FIXED_CTR00x0309
#define MSR_CORE_PERF_FIXED_CTR10x030a
#define MSR_CORE_PERF_FIXED_CTR20x030b
#define
Hi Stephane,
On 2007.06.21 01:36:45 -0700, Stephane Eranian wrote:
> Bjorn,
>
>
> On Wed, Jun 20, 2007 at 02:59:33PM -0700, Stephane Eranian wrote:
> > Bjorn,
> >
> > I ran into one issue related with the new allocator.
Should be the same with 2.6.21 and earlier, the "new" allocator should
do
Hi Stephane,
On 2007.06.21 01:36:45 -0700, Stephane Eranian wrote:
Bjorn,
On Wed, Jun 20, 2007 at 02:59:33PM -0700, Stephane Eranian wrote:
Bjorn,
I ran into one issue related with the new allocator.
Should be the same with 2.6.21 and earlier, the new allocator should
do exactly the
Bjorn,
You have the following registers to consider (for P4/Core):
#define MSR_IA32_PEBS_ENABLE0x03f1
#define MSR_CORE_PERF_FIXED_CTR00x0309
#define MSR_CORE_PERF_FIXED_CTR10x030a
#define MSR_CORE_PERF_FIXED_CTR20x030b
#define
Bjorn,
On Wed, Jun 20, 2007 at 02:59:33PM -0700, Stephane Eranian wrote:
> Bjorn,
>
> I ran into one issue related with the new allocator.
>
> In the case of a Core 2 Duo processor, the PMU implements more
> than just basic counters. In particular it supports fixed counters
> and PEBS where
Bjorn,
On Wed, Jun 20, 2007 at 02:59:33PM -0700, Stephane Eranian wrote:
Bjorn,
I ran into one issue related with the new allocator.
In the case of a Core 2 Duo processor, the PMU implements more
than just basic counters. In particular it supports fixed counters
and PEBS where both use
Bjorn,
I ran into one issue related with the new allocator.
In the case of a Core 2 Duo processor, the PMU implements more
than just basic counters. In particular it supports fixed counters
and PEBS where both use another set of MSRs. Those are not within
a 66 bit distance from
On 2007.06.20 15:01:02 +0200, Andi Kleen wrote:
>
> > Once this is fixed (which is what Bjorn did), then I will agree with you.
> > For this, the allocator needs to be able to probe the CPU and initialize
> > its own data structures.
>
> Ok that sounds reasonable. Please someone send a patch
> Once this is fixed (which is what Bjorn did), then I will agree with you.
> For this, the allocator needs to be able to probe the CPU and initialize
> its own data structures.
Ok that sounds reasonable. Please someone send a patch that does only
that.
-Andi
-
To unsubscribe from this list:
Andi,
On Wed, Jun 20, 2007 at 02:31:43PM +0200, Andi Kleen wrote:
> On Wednesday 20 June 2007 12:35:56 Björn Steinbrink wrote:
> > The performance counter allocator is tied to the LAPIC NMI watchdog,
>
> That's not true. It's completely independent. It just happens to be in
> the same file, but
Andi,
On Wed, Jun 20, 2007 at 02:31:43PM +0200, Andi Kleen wrote:
On Wednesday 20 June 2007 12:35:56 Björn Steinbrink wrote:
The performance counter allocator is tied to the LAPIC NMI watchdog,
That's not true. It's completely independent. It just happens to be in
the same file, but it has
Once this is fixed (which is what Bjorn did), then I will agree with you.
For this, the allocator needs to be able to probe the CPU and initialize
its own data structures.
Ok that sounds reasonable. Please someone send a patch that does only
that.
-Andi
-
To unsubscribe from this list: send
On 2007.06.20 15:01:02 +0200, Andi Kleen wrote:
Once this is fixed (which is what Bjorn did), then I will agree with you.
For this, the allocator needs to be able to probe the CPU and initialize
its own data structures.
Ok that sounds reasonable. Please someone send a patch that does
Bjorn,
I ran into one issue related with the new allocator.
In the case of a Core 2 Duo processor, the PMU implements more
than just basic counters. In particular it supports fixed counters
and PEBS where both use another set of MSRs. Those are not within
a 66 bit distance from
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