Re: [v4] PCI: Avoid unsync of LTR mechanism configuration

2021-03-21 Thread Mingchuang Qiao
Hi Bjorn, On Thu, 2021-02-18 at 10:50 -0600, Bjorn Helgaas wrote: > On Thu, Feb 04, 2021 at 05:51:25PM +0800, mingchuang.q...@mediatek.com wrote: > > From: Mingchuang Qiao > > > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > > configured in pci_configure_ltr(). If

Re: [v4] PCI: Avoid unsync of LTR mechanism configuration

2021-02-18 Thread Bjorn Helgaas
On Thu, Feb 04, 2021 at 05:51:25PM +0800, mingchuang.q...@mediatek.com wrote: > From: Mingchuang Qiao > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > configured in pci_configure_ltr(). If device and bridge both support LTR > mechanism, the "LTR Mechanism Enable" bit

Re: [v4] PCI: Avoid unsync of LTR mechanism configuration

2021-02-04 Thread Mika Westerberg
On Thu, Feb 04, 2021 at 05:51:25PM +0800, mingchuang.q...@mediatek.com wrote: > From: Mingchuang Qiao > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > configured in pci_configure_ltr(). If device and bridge both support LTR > mechanism, the "LTR Mechanism Enable" bit

[v4] PCI: Avoid unsync of LTR mechanism configuration

2021-02-04 Thread mingchuang.qiao
From: Mingchuang Qiao In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is configured in pci_configure_ltr(). If device and bridge both support LTR mechanism, the "LTR Mechanism Enable" bit of device and bridge will be enabled in DEVCTL2 register. And pci_dev->ltr_path will be