Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-06-06 Thread Hanjun Guo
On 2017/5/17 18:13, Shameerali Kolothum Thodi wrote: #ifdef CONFIG_ACPI +static void acpi_smmu_get_options(u32 model, struct arm_smmu_device +*smmu) { + if (model == ACPI_IORT_SMMU_CAVIUM_CN99XX) + smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; > HiSIlicon hip06/07 boards

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-06-06 Thread Hanjun Guo
On 2017/5/17 18:13, Shameerali Kolothum Thodi wrote: #ifdef CONFIG_ACPI +static void acpi_smmu_get_options(u32 model, struct arm_smmu_device +*smmu) { + if (model == ACPI_IORT_SMMU_CAVIUM_CN99XX) + smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; > HiSIlicon hip06/07 boards

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-18 Thread Geetha Akula
On Tue, May 16, 2017 at 5:45 AM, Rob Herring wrote: > DT changes should go to DT list. > > On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya > wrote: >> From: Linu Cherian >> >> Cavium ThunderX2 SMMU implementation doesn't

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-18 Thread Geetha Akula
On Tue, May 16, 2017 at 5:45 AM, Rob Herring wrote: > DT changes should go to DT list. > > On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya > wrote: >> From: Linu Cherian >> >> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space >> and PAGE0_REGS_ONLY option is enabled as

RE: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-17 Thread Shameerali Kolothum Thodi
..@vger.kernel.org; > robert.rich...@cavium.com; lv.zh...@intel.com; catalin.mari...@arm.com; > sgout...@cavium.com; linux-arm-ker...@lists.infradead.org; > de...@acpica.org > Subject: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium > ThunderX2 erratum #74 > > From: Linu C

RE: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-17 Thread Shameerali Kolothum Thodi
..@vger.kernel.org; > robert.rich...@cavium.com; lv.zh...@intel.com; catalin.mari...@arm.com; > sgout...@cavium.com; linux-arm-ker...@lists.infradead.org; > de...@acpica.org > Subject: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium > ThunderX2 erratum #74 > > From: L

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-15 Thread Rob Herring
DT changes should go to DT list. On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-15 Thread Rob Herring
DT changes should go to DT list. On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > This option when turned on, replaces

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-12 Thread kbuild test robot
Hi Linu, [auto build test ERROR on arm64/for-next/core] [also build test ERROR on v4.11 next-20170512] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-12 Thread kbuild test robot
Hi Linu, [auto build test ERROR on arm64/for-next/core] [also build test ERROR on v4.11 next-20170512] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

[v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-12 Thread Geetha sowjanya
From: Linu Cherian Cavium ThunderX2 SMMU implementation doesn't support page 1 register space and PAGE0_REGS_ONLY option is enabled as an errata workaround. This option when turned on, replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access

[v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

2017-05-12 Thread Geetha sowjanya
From: Linu Cherian Cavium ThunderX2 SMMU implementation doesn't support page 1 register space and PAGE0_REGS_ONLY option is enabled as an errata workaround. This option when turned on, replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. SMMU