On 2017/5/17 18:13, Shameerali Kolothum Thodi wrote:
#ifdef CONFIG_ACPI
+static void acpi_smmu_get_options(u32 model, struct arm_smmu_device
+*smmu) {
+ if (model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
+ smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY;
>
HiSIlicon hip06/07 boards
On 2017/5/17 18:13, Shameerali Kolothum Thodi wrote:
#ifdef CONFIG_ACPI
+static void acpi_smmu_get_options(u32 model, struct arm_smmu_device
+*smmu) {
+ if (model == ACPI_IORT_SMMU_CAVIUM_CN99XX)
+ smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY;
>
HiSIlicon hip06/07 boards
On Tue, May 16, 2017 at 5:45 AM, Rob Herring wrote:
> DT changes should go to DT list.
>
> On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
> wrote:
>> From: Linu Cherian
>>
>> Cavium ThunderX2 SMMU implementation doesn't
On Tue, May 16, 2017 at 5:45 AM, Rob Herring wrote:
> DT changes should go to DT list.
>
> On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
> wrote:
>> From: Linu Cherian
>>
>> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
>> and PAGE0_REGS_ONLY option is enabled as
..@vger.kernel.org;
> robert.rich...@cavium.com; lv.zh...@intel.com; catalin.mari...@arm.com;
> sgout...@cavium.com; linux-arm-ker...@lists.infradead.org;
> de...@acpica.org
> Subject: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium
> ThunderX2 erratum #74
>
> From: Linu C
..@vger.kernel.org;
> robert.rich...@cavium.com; lv.zh...@intel.com; catalin.mari...@arm.com;
> sgout...@cavium.com; linux-arm-ker...@lists.infradead.org;
> de...@acpica.org
> Subject: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium
> ThunderX2 erratum #74
>
> From: L
DT changes should go to DT list.
On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option is enabled as an errata
DT changes should go to DT list.
On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya
wrote:
> From: Linu Cherian
>
> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option is enabled as an errata workaround.
> This option when turned on, replaces
Hi Linu,
[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.11 next-20170512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi Linu,
[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.11 next-20170512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
From: Linu Cherian
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access
From: Linu Cherian
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
SMMU
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