Re: Haswell mem-store question

2014-05-14 Thread Andi Kleen
> I think it should do: > > if (status & 1) > dse.mem_lvl = PERF_MEM_LVL_L1|PERF_MEM_LVL_HIT; > else > dse.mem_lvl = PERF_MEM_LVL_L1|PERF_MEM_LVL_MISS; > > Otherwise you have L1 as the level with no hit/miss info. Agreed. BTW the line before is also not always corect, and any ev

Re: Haswell mem-store question

2014-05-14 Thread Stephane Eranian
On Wed, May 14, 2014 at 10:50 PM, Don Zickus wrote: > > Hi Andi, > > Joe was playing with our c2c tool today and noticed we were losing store > events from perf's mem-stores event. Upon investigation we stumbled into > some differences in data that Haswell reports vs. Ivy/Sandy Bridge. > > This l

Haswell mem-store question

2014-05-14 Thread Don Zickus
Hi Andi, Joe was playing with our c2c tool today and noticed we were losing store events from perf's mem-stores event. Upon investigation we stumbled into some differences in data that Haswell reports vs. Ivy/Sandy Bridge. This leaves our tool needing two different paths depending on the archite