On 27/05/2020 01:09, Andy Lutomirski wrote:
> [cc Andrew Cooper and Dave Hansen]
>
> On Fri, May 15, 2020 at 7:35 PM Nicholas Piggin wrote:
>> Excerpts from Rik van Riel's message of May 16, 2020 5:24 am:
>>> On Fri, 2020-05-15 at 16:50 +1000, Nicholas Piggin wrote:
But what about if there
[cc Andrew Cooper and Dave Hansen]
On Fri, May 15, 2020 at 7:35 PM Nicholas Piggin wrote:
>
> Excerpts from Rik van Riel's message of May 16, 2020 5:24 am:
> > On Fri, 2020-05-15 at 16:50 +1000, Nicholas Piggin wrote:
> >>
> >> But what about if there are (real, not speculative) stores in the
>
Excerpts from Rik van Riel's message of May 16, 2020 5:24 am:
> On Fri, 2020-05-15 at 16:50 +1000, Nicholas Piggin wrote:
>>
>> But what about if there are (real, not speculative) stores in the
>> store
>> queue still on the lazy thread from when it was switched, that have
>> not
>> yet become
On Fri, 2020-05-15 at 16:50 +1000, Nicholas Piggin wrote:
>
> But what about if there are (real, not speculative) stores in the
> store
> queue still on the lazy thread from when it was switched, that have
> not
> yet become coherent? The page is freed by another CPU and reallocated
> for
Hi Rik,
Commit 145f573b89a62 ("Make lazy TLB mode lazier").
A couple of questions here (and I don't know the x86 architecture too
well let alone the ASID stuff, so bear with me). I'm assuming, and it
appears to be in the x86 manual that you can't map the same physical
page with conflicting
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