kernel.org; Alexandre Belloni; Boris BREZILLON
> Subject: Re: [PATCH RESEND] pm: at91: Workaround DDRSDRC self-refresh bug
> with LPDDR1 memories
>
> Le 14/01/2015 14:20, Peter Rosin a écrit :
> > From: Peter Rosin
> >
> > The DDRSDR controller (on the ATSAMA5D31) fails m
Nicolas Ferre wrote:
> Le 14/01/2015 14:20, Peter Rosin a écrit :
> > From: Peter Rosin
> >
> > The DDRSDR controller (on the ATSAMA5D31) fails miserably to put
> > LPDDR1 memories in self-refresh. Force the controller to think it has
> > DDR2 memories during the self-refresh period, as the DDR2
Le 14/01/2015 14:20, Peter Rosin a écrit :
> From: Peter Rosin
>
> The DDRSDR controller (on the ATSAMA5D31) fails miserably to put LPDDR1
> memories in self-refresh. Force the controller to think it has DDR2
> memories during the self-refresh period, as the DDR2 self-refresh spec
> is
Nicolas Ferre wrote:
Le 14/01/2015 14:20, Peter Rosin a écrit :
From: Peter Rosin p...@axentia.se
The DDRSDR controller (on the ATSAMA5D31) fails miserably to put
LPDDR1 memories in self-refresh. Force the controller to think it has
DDR2 memories during the self-refresh period, as the
; Boris BREZILLON
Subject: Re: [PATCH RESEND] pm: at91: Workaround DDRSDRC self-refresh bug
with LPDDR1 memories
Le 14/01/2015 14:20, Peter Rosin a écrit :
From: Peter Rosin p...@axentia.se
The DDRSDR controller (on the ATSAMA5D31) fails miserably to put
LPDDR1 memories in self-refresh
Le 14/01/2015 14:20, Peter Rosin a écrit :
From: Peter Rosin p...@axentia.se
The DDRSDR controller (on the ATSAMA5D31) fails miserably to put LPDDR1
memories in self-refresh. Force the controller to think it has DDR2
memories during the self-refresh period, as the DDR2 self-refresh spec
is
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