> From: Peng Fan <peng....@nxp.com>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> Add i.MX7ULP pmc node for m4 and a7.
>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> ---
> arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> index b7ea37ad4e55..b02dc4c97fb8 100644
> --- a/arch/arm/boot/dts/imx7ulp.dtsi
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -286,6 +286,11 @@ pcc2: clock-controller@403f0000 {
> assigned-clock-parents = <&scg1
> IMX7ULP_CLK_SOSC_BUS_CLK>;
> };
>
> + pmc1: pmc1@40400000 {
s/pmc1/pmc
> + compatible = "fsl,imx7ulp-pmc1";
> + reg = <0x40400000 0x1000>;
> + };
> +
> smc1: clock-controller@40410000 {
> compatible = "fsl,imx7ulp-smc1";
> reg = <0x40410000 0x1000>;
> @@ -447,6 +452,11 @@ m4aips1: bus@41080000 {
> reg = <0x41080000 0x80000>;
> ranges;
>
> + pmc0: pmc0@410a1000 {
s/pmc0/pmc
> + compatible = "fsl,imx7ulp-pmc0";
> + reg = <0x410a1000 0x1000>;
> + };
> +
> sim: sim@410a3000 {
> compatible = "fsl,imx7ulp-sim", "syscon";
> reg = <0x410a3000 0x1000>;
> --
> 2.28.0
