Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On 18.12.2017 15:05, Arnd Bergmann wrote: > On Mon, Dec 18, 2017 at 2:13 PM, Michal Simek wrote: >> On 15.12.2017 14:26, Arnd Bergmann wrote: >>> In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: Xilinx ZYNQMP logicoreIP Init driver is

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On 18.12.2017 15:05, Arnd Bergmann wrote: > On Mon, Dec 18, 2017 at 2:13 PM, Michal Simek wrote: >> On 15.12.2017 14:26, Arnd Bergmann wrote: >>> In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Mon, Dec 18, 2017 at 2:13 PM, Michal Simek wrote: > On 15.12.2017 14:26, Arnd Bergmann wrote: >> In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: >>> Xilinx ZYNQMP logicoreIP Init driver is based on the new >>> LogiCoreIP design created.

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Mon, Dec 18, 2017 at 2:13 PM, Michal Simek wrote: > On 15.12.2017 14:26, Arnd Bergmann wrote: >> In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: >>> Xilinx ZYNQMP logicoreIP Init driver is based on the new >>> LogiCoreIP design created. This driver provides the processing system >>> and

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On 15.12.2017 14:26, Arnd Bergmann wrote: > In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: >> Xilinx ZYNQMP logicoreIP Init driver is based on the new >> LogiCoreIP design created. This driver provides the processing system >> and programmable logic isolation. Set the

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On 15.12.2017 14:26, Arnd Bergmann wrote: > In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: >> Xilinx ZYNQMP logicoreIP Init driver is based on the new >> LogiCoreIP design created. This driver provides the processing system >> and programmable logic isolation. Set the frequency based on the

RE: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

arm.com > Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com> > Subject: Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP > init driver > > On 12/16/2017 10:07 PM, Dhaval Rajeshbhai Shah wrote: >

RE: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

.org; linux-kernel@vger.kernel.org; > michal.si...@xilinx.com; Hyun Kwon > Subject: Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP > init driver > > On 12/16/2017 10:07 PM, Dhaval Rajeshbhai Shah wrote: > > Hi Randy, > > > > Thanks a

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

ah <ds...@xilinx.com>; a...@arndb.de; >> gre...@linuxfoundation.org; robh...@kernel.org; mark.rutl...@arm.com >> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >> michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai >> Shah <

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

eshbhai Shah ; a...@arndb.de; >> gre...@linuxfoundation.org; robh...@kernel.org; mark.rutl...@arm.com >> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; >> michal.si...@xilinx.com; Hyun Kwon ; Dhaval Rajeshbhai >> Shah >> Subject: Re: [PATCH v4 2/2] misc: xlnx_vcu: A

RE: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

kernel.org; mark.rutl...@arm.com > Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai > Shah <ds...@xilinx.com> > Subject: Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP >

RE: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

m > Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > michal.si...@xilinx.com; Hyun Kwon ; Dhaval Rajeshbhai > Shah > Subject: Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP > init driver > > On 12/14/2017 11:24 PM, Dhaval Shah wrote: >

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On 12/14/2017 11:24 PM, Dhaval Shah wrote: > Xilinx ZYNQMP logicoreIP Init driver is based on the new > LogiCoreIP design created. This driver provides the processing system > and programmable logic isolation. Set the frequency based on the clock > information get from the logicoreIP register set.

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

On 12/14/2017 11:24 PM, Dhaval Shah wrote: > Xilinx ZYNQMP logicoreIP Init driver is based on the new > LogiCoreIP design created. This driver provides the processing system > and programmable logic isolation. Set the frequency based on the clock > information get from the logicoreIP register set.

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: > Xilinx ZYNQMP logicoreIP Init driver is based on the new > LogiCoreIP design created. This driver provides the processing system > and programmable logic isolation. Set the frequency based on the clock > information get

Re: [PATCH v4 2/2] misc: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver

In Fri, Dec 15, 2017 at 8:24 AM, Dhaval Shah wrote: > Xilinx ZYNQMP logicoreIP Init driver is based on the new > LogiCoreIP design created. This driver provides the processing system > and programmable logic isolation. Set the frequency based on the clock > information get from the logicoreIP