rg; linux-...@vger.kernel.org; Marek Vasut
>>>> ; Mark Brown ; Han Xu
>>>> ; dw...@infradead.org;
>> computersforpe...@gmail.com;
>>>> rich...@nod.at; miquel.ray...@bootlin.com; David Wolfe
>>>> ; Fabio Estevam ;
>>>> Prabhakar Kush
rg; linux-...@vger.kernel.org; Marek Vasut
>>>> ; Mark Brown ; Han Xu
>>>> ; dw...@infradead.org;
>> computersforpe...@gmail.com;
>>>> rich...@nod.at; miquel.ray...@bootlin.com; David Wolfe
>>>> ; Fabio Estevam ;
>>>> Prabhakar Kush
Mark
> Brown ; Han Xu ;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 3/9] spi: Add a driver
Mark
> Brown ; Han Xu ;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 3/9] spi: Add a driver
gt;> ; shawn...@kernel.org; linux-
>> ker...@vger.kernel.org
>> Subject: Re: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
>> controller
>>
>> Hi Yogesh,
>>
>> On 15.11.18 14:12, Boris Brezillon wrote:
>>> On Thu
gt;> ; shawn...@kernel.org; linux-
>> ker...@vger.kernel.org
>> Subject: Re: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
>> controller
>>
>> Hi Yogesh,
>>
>> On 15.11.18 14:12, Boris Brezillon wrote:
>>> On Thu
Mark
> Brown ; Han Xu ;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 3/9] spi: Add a driver
Mark
> Brown ; Han Xu ;
> dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 3/9] spi: Add a driver
Hi Yogesh,
On 15.11.18 14:12, Boris Brezillon wrote:
> On Thu, 15 Nov 2018 11:43:05 +
> Schrempf Frieder wrote:
>
>> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
>>> Hi Frieder,
>>>
>>> With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
>>> for me.
>>
>> Ok, are
Hi Yogesh,
On 15.11.18 14:12, Boris Brezillon wrote:
> On Thu, 15 Nov 2018 11:43:05 +
> Schrempf Frieder wrote:
>
>> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
>>> Hi Frieder,
>>>
>>> With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
>>> for me.
>>
>> Ok, are
On Thu, 15 Nov 2018 11:43:05 +
Schrempf Frieder wrote:
> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> > Hi Frieder,
> >
> > With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
> > for me.
>
> Ok, are you sure, that AHB read is working too with this patch?
>
On Thu, 15 Nov 2018 11:43:05 +
Schrempf Frieder wrote:
> On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> > Hi Frieder,
> >
> > With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
> > for me.
>
> Ok, are you sure, that AHB read is working too with this patch?
>
On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
> for me.
Ok, are you sure, that AHB read is working too with this patch?
You are removing the memmap_phy offset from SFAR and the SFXXAD register
values.
On 15.11.18 07:22, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> With below patch on top of your v5, Read/Write/Erase on CS1 is working fine
> for me.
Ok, are you sure, that AHB read is working too with this patch?
You are removing the memmap_phy offset from SFAR and the SFXXAD register
values.
Hi Frieder,
With below patch on top of your v5, Read/Write/Erase on CS1 is working fine for
me.
I have tested with JFFS2 mounting and booting also for both CS0 and CS1.
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index ce45e8e..4467983 100644
---
Hi Frieder,
With below patch on top of your v5, Read/Write/Erase on CS1 is working fine for
me.
I have tested with JFFS2 mounting and booting also for both CS0 and CS1.
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index ce45e8e..4467983 100644
---
On 14.11.18 11:43, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> [..]
>>>
>>> Ok, I will have a look at what could make the chip selection fail in
>>> case of AHB read.
>>
>> Could you try with this change applied:
>>
>> @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q,
>>
On 14.11.18 11:43, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> [..]
>>>
>>> Ok, I will have a look at what could make the chip selection fail in
>>> case of AHB read.
>>
>> Could you try with this change applied:
>>
>> @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q,
>>
On Wed, 14 Nov 2018 10:43:00 +
Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> [..]
> > >
> > > Ok, I will have a look at what could make the chip selection fail in
> > > case of AHB read.
> >
> > Could you try with this change applied:
> >
> > @@ -503,7 +503,7 @@ static void
On Wed, 14 Nov 2018 10:43:00 +
Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> [..]
> > >
> > > Ok, I will have a look at what could make the chip selection fail in
> > > case of AHB read.
> >
> > Could you try with this change applied:
> >
> > @@ -503,7 +503,7 @@ static void
Hi Frieder,
[..]
> >
> > Ok, I will have a look at what could make the chip selection fail in
> > case of AHB read.
>
> Could you try with this change applied:
>
> @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct
> spi_device *spi)
>
Hi Frieder,
[..]
> >
> > Ok, I will have a look at what could make the chip selection fail in
> > case of AHB read.
>
> Could you try with this change applied:
>
> @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct
> spi_device *spi)
>
Hi Yogesh,
On 14.11.18 09:50, Frieder Schrempf wrote:
> Hi Yogesh,
>
> On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
>> Hi Frieder,
>>
>> I have tried v5 version of the patch and have observed that Read is
>> failing for CS1.
>
> Thanks a lot for doing the test. I really appreciate it.
>
>>
Hi Yogesh,
On 14.11.18 09:50, Frieder Schrempf wrote:
> Hi Yogesh,
>
> On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
>> Hi Frieder,
>>
>> I have tried v5 version of the patch and have observed that Read is
>> failing for CS1.
>
> Thanks a lot for doing the test. I really appreciate it.
>
>>
Hi Yogesh,
On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> I have tried v5 version of the patch and have observed that Read is failing
> for CS1.
Thanks a lot for doing the test. I really appreciate it.
> In my target 2 flash devices are connected on same bus i.e. A1 -> CS0
Hi Yogesh,
On 14.11.18 09:39, Yogesh Narayan Gaur wrote:
> Hi Frieder,
>
> I have tried v5 version of the patch and have observed that Read is failing
> for CS1.
Thanks a lot for doing the test. I really appreciate it.
> In my target 2 flash devices are connected on same bus i.e. A1 -> CS0
Hi Frieder,
I have tried v5 version of the patch and have observed that Read is failing for
CS1.
In my target 2 flash devices are connected on same bus i.e. A1 -> CS0 and A2 ->
CS1.
On initial debugging, I figured that Read is failing for the AHB mode i.e. if I
attempt to read data size less
Hi Frieder,
I have tried v5 version of the patch and have observed that Read is failing for
CS1.
In my target 2 flash devices are connected on same bus i.e. A1 -> CS0 and A2 ->
CS1.
On initial debugging, I figured that Read is failing for the AHB mode i.e. if I
attempt to read data size less
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